[PATCH] D28810: [X86][SSE] Use MOVMSK for all_of/any_of reduction patterns

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon marked an inline comment as done.
RKSimon added a comment.

I've limited the combine to only reduce vectors with 4 or more elements.



================
Comment at: lib/Target/X86/X86ISelLowering.cpp:28639
+    SDValue Match = matchBinOpReduction(Extract, Op);
+    if (!Match || (Match.getScalarValueSizeInBits() != BitWidth))
+      continue;
----------------
filcab wrote:
> Maybe that second part should be in an assert?
> The way I see it, we haven't really done much yet, so either:
>   - The bitwidth changed (how? `matchBinOpReduction` bails if it encounters an extract_subvector (shuffles with different sizes are a thing in IR though, can't remember if also on SDAG)) but we can still recover if we use the new bitwidth we got (if it still matched, there shouldn't be a big problem, no?)
>   - The bitwidth changed and we can't recover (does this happen?)
So there are valid situations where Match.getScalarValueSizeInBits() != BitWidth as EXTRACT_VECTOR_ELT can perform implicit extension of the extracted vector element. I've added a comment to explain. If it proves useful we can add support for this case but don't see a need yet.


Repository:
  rL LLVM

https://reviews.llvm.org/D28810