[llvm] r292629 - ARM: tLDR_postidx should be marked mayLoad

Matthias Braun via llvm-commits llvm-commits at lists.llvm.org
Fri Jan 20 10:30:28 PST 2017


Author: matze
Date: Fri Jan 20 12:30:28 2017
New Revision: 292629

URL: http://llvm.org/viewvc/llvm-project?rev=292629&view=rev
Log:
ARM: tLDR_postidx should be marked mayLoad

This fixes -verify-machineinstrs complaints.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrThumb.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=292629&r1=292628&r2=292629&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Fri Jan 20 12:30:28 2017
@@ -1477,7 +1477,7 @@ def : T1Pat<(extloadi16 t_addrmode_rr:$a
 // post-inc LDR -> LDM r0!, {r1}. The way operands are layed out in LDMs is
 // different to how ISel expects them for a post-inc load, so use a pseudo
 // and expand it just after ISel.
-let usesCustomInserter = 1,
+let usesCustomInserter = 1, mayLoad =1,
     Constraints = "$Rn = $Rn_wb, at earlyclobber $Rn_wb" in
  def tLDR_postidx: tPseudoInst<(outs rGPR:$Rt, rGPR:$Rn_wb),
                                (ins rGPR:$Rn, pred:$p),




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