[PATCH] D28194: [ARM] Classification Improvements to ARM Sched-Models. NFCI.

[Diana Picus via Phabricator via llvm-commits]

rovka added a comment.

Hi Javed,

Sorry about the delay, I was out of office for a few days. Comments below.

Cheers,
Diana



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Comment at: lib/Target/ARM/ARMInstrVFP.td:402
+                  []>,
+             Sched<[WriteFPDIV32]>;
 
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Why are half precision division and multiplication modeled the same as single precision, but half precision add/sub/sqrt aren't?


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Comment at: lib/Target/ARM/ARMSchedule.td:58
+//===----------------------------------------------------------------------===//
+// Sched definitions for intger pipeline instructions
+//
----------------
Typo: integer


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Comment at: lib/Target/ARM/ARMScheduleA9.td:1948
 
+def : WriteRes<WriteFPDIV32, [A9UnitFP, A9UnitAGU]> { let Latency = 15; }
+def : WriteRes<WriteFPDIV64, [A9UnitFP, A9UnitAGU]> { let Latency = 25; }
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Why isn't this just a SchedAlias for A9WriteFDivS?


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Comment at: lib/Target/ARM/ARMScheduleA9.td:2554
 def : WriteRes<WritePreLd, []>;
-def : SchedAlias<WriteCvtFP, A9WriteF>;
+//def : SchedAlias<WriteCvtFP, A9WriteF>;
 def : WriteRes<WriteNoop, []> { let Latency = 0; let NumMicroOps = 0; }
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Missed a spot.


https://reviews.llvm.org/D28194