[PATCH] D28805: [GlobalISel] Pointers are legal operands for G_SELECT on AArch64

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This revision was automatically updated to reflect the committed changes.
Closed by commit rL292481: [GlobalISel] Pointers are legal operands for G_SELECT on AArch64 (authored by kbeyls).

Changed prior to commit:
  https://reviews.llvm.org/D28805?vs=84666&id=84959#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D28805

Files:
  llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp
  llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp
  llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir


Index: llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir
===================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir
@@ -2950,20 +2950,28 @@
 # CHECK-NEXT:  - { id: 4, class: gpr64 }
 # CHECK-NEXT:  - { id: 5, class: gpr64 }
 # CHECK-NEXT:  - { id: 6, class: gpr64 }
+# CHECK-NEXT:  - { id: 7, class: gpr64 }
+# CHECK-NEXT:  - { id: 8, class: gpr64 }
+# CHECK-NEXT:  - { id: 9, class: gpr64 }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
   - { id: 4, class: gpr }
   - { id: 5, class: gpr }
   - { id: 6, class: gpr }
+  - { id: 7, class: gpr }
+  - { id: 8, class: gpr }
+  - { id: 9, class: gpr }
 
 # CHECK:  body:
 # CHECK:      %wzr = ANDSWri %0, 0, implicit-def %nzcv
 # CHECK:      %3 = CSELWr %1, %2, 1, implicit %nzcv
 # CHECK:      %wzr = ANDSWri %0, 0, implicit-def %nzcv
 # CHECK:      %6 = CSELXr %4, %5, 1, implicit %nzcv
+# CHECK:      %wzr = ANDSWri %0, 0, implicit-def %nzcv
+# CHECK:      %9 = CSELXr %7, %8, 1, implicit %nzcv
 body:             |
   bb.0:
     liveins: %w0, %w1, %w2
@@ -2976,4 +2984,8 @@
     %4(s64) = COPY %x0
     %5(s64) = COPY %x1
     %6(s64) = G_SELECT %0, %4, %5
+
+    %7(p0) = COPY %x0
+    %8(p0) = COPY %x1
+    %9(p0) = G_SELECT %0, %7, %8
 ...
Index: llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp
===================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp
+++ llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp
@@ -1026,7 +1026,7 @@
 
     if (Ty == LLT::scalar(32)) {
       CSelOpc = AArch64::CSELWr;
-    } else if (Ty == LLT::scalar(64)) {
+    } else if (Ty == LLT::scalar(64) || Ty == LLT::pointer(0, 64)) {
       CSelOpc = AArch64::CSELXr;
     } else {
       return false;
Index: llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp
===================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp
+++ llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp
@@ -160,7 +160,7 @@
     setAction({G_BRCOND, Ty}, Legal);
 
   // Select
-  for (auto Ty : {s1, s8, s16, s32, s64})
+  for (auto Ty : {s1, s8, s16, s32, s64, p0})
     setAction({G_SELECT, Ty}, Legal);
 
   setAction({G_SELECT, 1, s1}, Legal);


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