[llvm] r292481 - [GlobalISel] Pointers are legal operands for G_SELECT on AArch64
Kristof Beyls via llvm-commits
llvm-commits at lists.llvm.org
Thu Jan 19 05:32:14 PST 2017
Author: kbeyls
Date: Thu Jan 19 07:32:14 2017
New Revision: 292481
URL: http://llvm.org/viewvc/llvm-project?rev=292481&view=rev
Log:
[GlobalISel] Pointers are legal operands for G_SELECT on AArch64
Differential Revision: https://reviews.llvm.org/D28805
Modified:
llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp
llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp
llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir
Modified: llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp?rev=292481&r1=292480&r2=292481&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp Thu Jan 19 07:32:14 2017
@@ -1026,7 +1026,7 @@ bool AArch64InstructionSelector::select(
if (Ty == LLT::scalar(32)) {
CSelOpc = AArch64::CSELWr;
- } else if (Ty == LLT::scalar(64)) {
+ } else if (Ty == LLT::scalar(64) || Ty == LLT::pointer(0, 64)) {
CSelOpc = AArch64::CSELXr;
} else {
return false;
Modified: llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp?rev=292481&r1=292480&r2=292481&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp Thu Jan 19 07:32:14 2017
@@ -160,7 +160,7 @@ AArch64LegalizerInfo::AArch64LegalizerIn
setAction({G_BRCOND, Ty}, Legal);
// Select
- for (auto Ty : {s1, s8, s16, s32, s64})
+ for (auto Ty : {s1, s8, s16, s32, s64, p0})
setAction({G_SELECT, Ty}, Legal);
setAction({G_SELECT, 1, s1}, Legal);
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir?rev=292481&r1=292480&r2=292481&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir Thu Jan 19 07:32:14 2017
@@ -2950,6 +2950,9 @@ tracksRegLiveness: true
# CHECK-NEXT: - { id: 4, class: gpr64 }
# CHECK-NEXT: - { id: 5, class: gpr64 }
# CHECK-NEXT: - { id: 6, class: gpr64 }
+# CHECK-NEXT: - { id: 7, class: gpr64 }
+# CHECK-NEXT: - { id: 8, class: gpr64 }
+# CHECK-NEXT: - { id: 9, class: gpr64 }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@@ -2958,12 +2961,17 @@ registers:
- { id: 4, class: gpr }
- { id: 5, class: gpr }
- { id: 6, class: gpr }
+ - { id: 7, class: gpr }
+ - { id: 8, class: gpr }
+ - { id: 9, class: gpr }
# CHECK: body:
# CHECK: %wzr = ANDSWri %0, 0, implicit-def %nzcv
# CHECK: %3 = CSELWr %1, %2, 1, implicit %nzcv
# CHECK: %wzr = ANDSWri %0, 0, implicit-def %nzcv
# CHECK: %6 = CSELXr %4, %5, 1, implicit %nzcv
+# CHECK: %wzr = ANDSWri %0, 0, implicit-def %nzcv
+# CHECK: %9 = CSELXr %7, %8, 1, implicit %nzcv
body: |
bb.0:
liveins: %w0, %w1, %w2
@@ -2976,4 +2984,8 @@ body: |
%4(s64) = COPY %x0
%5(s64) = COPY %x1
%6(s64) = G_SELECT %0, %4, %5
+
+ %7(p0) = COPY %x0
+ %8(p0) = COPY %x1
+ %9(p0) = G_SELECT %0, %7, %8
...
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