[llvm] r292478 - Re-commit: [globalisel] Tablegen-erate current Register Bank Information
Daniel Sanders via llvm-commits
llvm-commits at lists.llvm.org
Thu Jan 19 03:15:56 PST 2017
Author: dsanders
Date: Thu Jan 19 05:15:55 2017
New Revision: 292478
URL: http://llvm.org/viewvc/llvm-project?rev=292478&view=rev
Log:
Re-commit: [globalisel] Tablegen-erate current Register Bank Information
Summary:
Adds a RegisterBank tablegen class that can be used to declare the register
banks and an associated tablegen pass to generate the necessary code.
Changes since first commit attempt:
* Added missing guards
* Added more missing guards
* Found and fixed a use-after-free bug involving Twine locals
Reviewers: t.p.northover, ab, rovka, qcolombet
Reviewed By: qcolombet
Subscribers: aditya_nandakumar, rengolin, kristof.beyls, vkalintiris, mgorny, dberris, llvm-commits, rovka
Differential Revision: https://reviews.llvm.org/D27338
Added:
llvm/trunk/include/llvm/Target/GlobalISel/
- copied from r292368, llvm/trunk/include/llvm/Target/GlobalISel/
llvm/trunk/lib/Target/AArch64/AArch64RegisterBanks.td
- copied unchanged from r292368, llvm/trunk/lib/Target/AArch64/AArch64RegisterBanks.td
llvm/trunk/llvm/
- copied from r292368, llvm/trunk/llvm/
llvm/trunk/utils/TableGen/RegisterBankEmitter.cpp
- copied, changed from r292368, llvm/trunk/utils/TableGen/RegisterBankEmitter.cpp
Modified:
llvm/trunk/include/llvm/CodeGen/GlobalISel/RegisterBank.h
llvm/trunk/include/llvm/Target/Target.td
llvm/trunk/lib/CodeGen/GlobalISel/RegisterBank.cpp
llvm/trunk/lib/Target/AArch64/AArch64.td
llvm/trunk/lib/Target/AArch64/AArch64GenRegisterBankInfo.def
llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.h
llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.cpp
llvm/trunk/lib/Target/AArch64/CMakeLists.txt
llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp
llvm/trunk/utils/TableGen/CMakeLists.txt
llvm/trunk/utils/TableGen/TableGen.cpp
llvm/trunk/utils/TableGen/TableGenBackends.h
Modified: llvm/trunk/include/llvm/CodeGen/GlobalISel/RegisterBank.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/GlobalISel/RegisterBank.h?rev=292478&r1=292477&r2=292478&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/GlobalISel/RegisterBank.h (original)
+++ llvm/trunk/include/llvm/CodeGen/GlobalISel/RegisterBank.h Thu Jan 19 05:15:55 2017
@@ -42,7 +42,7 @@ private:
public:
RegisterBank(unsigned ID, const char *Name, unsigned Size,
- const uint32_t *ContainedRegClasses);
+ const uint32_t *ContainedRegClasses, unsigned NumRegClasses);
/// Get the identifier of this register bank.
unsigned getID() const { return ID; }
Modified: llvm/trunk/include/llvm/Target/Target.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/Target.td?rev=292478&r1=292477&r2=292478&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/Target.td (original)
+++ llvm/trunk/include/llvm/Target/Target.td Thu Jan 19 05:15:55 2017
@@ -1344,4 +1344,5 @@ include "llvm/Target/TargetSelectionDAG.
//===----------------------------------------------------------------------===//
// Pull in the common support for Global ISel generation.
//
+include "llvm/Target/GlobalISel/RegisterBank.td"
include "llvm/Target/TargetGlobalISel.td"
Modified: llvm/trunk/lib/CodeGen/GlobalISel/RegisterBank.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/RegisterBank.cpp?rev=292478&r1=292477&r2=292478&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/GlobalISel/RegisterBank.cpp (original)
+++ llvm/trunk/lib/CodeGen/GlobalISel/RegisterBank.cpp Thu Jan 19 05:15:55 2017
@@ -19,10 +19,11 @@ using namespace llvm;
const unsigned RegisterBank::InvalidID = UINT_MAX;
-RegisterBank::RegisterBank(unsigned ID, const char *Name, unsigned Size,
- const uint32_t *CoveredClasses)
+RegisterBank::RegisterBank(
+ unsigned ID, const char *Name, unsigned Size,
+ const uint32_t *CoveredClasses, unsigned NumRegClasses)
: ID(ID), Name(Name), Size(Size) {
- ContainedRegClasses.resize(200);
+ ContainedRegClasses.resize(NumRegClasses);
ContainedRegClasses.setBitsInMask(CoveredClasses);
}
Modified: llvm/trunk/lib/Target/AArch64/AArch64.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64.td?rev=292478&r1=292477&r2=292478&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64.td Thu Jan 19 05:15:55 2017
@@ -127,6 +127,7 @@ def HasV8_2aOps : SubtargetFeature<"v8.2
//===----------------------------------------------------------------------===//
include "AArch64RegisterInfo.td"
+include "AArch64RegisterBanks.td"
include "AArch64CallingConvention.td"
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/lib/Target/AArch64/AArch64GenRegisterBankInfo.def
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64GenRegisterBankInfo.def?rev=292478&r1=292477&r2=292478&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64GenRegisterBankInfo.def (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64GenRegisterBankInfo.def Thu Jan 19 05:15:55 2017
@@ -16,204 +16,81 @@
#endif
namespace llvm {
-namespace AArch64 {
-
-const uint32_t GPRCoverageData[] = {
- // Classes 0-31
- (1u << AArch64::GPR32allRegClassID) | (1u << AArch64::GPR32RegClassID) |
- (1u << AArch64::GPR32spRegClassID) |
- (1u << AArch64::GPR32commonRegClassID) |
- (1u << AArch64::GPR32sponlyRegClassID) |
- (1u << AArch64::GPR64allRegClassID) | (1u << AArch64::GPR64RegClassID) |
- (1u << AArch64::GPR64spRegClassID) |
- (1u << AArch64::GPR64commonRegClassID) |
- (1u << AArch64::tcGPR64RegClassID) |
- (1u << AArch64::GPR64sponlyRegClassID),
- // Classes 32-63
- 0,
- // FIXME: The entries below this point can be safely removed once this is
- // tablegenerated. It's only needed because of the hardcoded register class
- // limit.
- // Classes 64-96
- 0,
- // Classes 97-128
- 0,
- // Classes 129-160
- 0,
- // Classes 161-192
- 0,
- // Classes 193-224
- 0,
-};
-
-const uint32_t FPRCoverageData[] = {
- // Classes 0-31
- (1u << AArch64::FPR8RegClassID) | (1u << AArch64::FPR16RegClassID) |
- (1u << AArch64::FPR32RegClassID) | (1u << AArch64::FPR64RegClassID) |
- (1u << AArch64::DDRegClassID) | (1u << AArch64::FPR128RegClassID) |
- (1u << AArch64::FPR128_loRegClassID) | (1u << AArch64::DDDRegClassID) |
- (1u << AArch64::DDDDRegClassID),
- // Classes 32-63
- (1u << (AArch64::QQRegClassID - 32)) |
- (1u << (AArch64::QQ_with_qsub0_in_FPR128_loRegClassID - 32)) |
- (1u << (AArch64::QQ_with_qsub1_in_FPR128_loRegClassID - 32)) |
- (1u
- << (AArch64::
- QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID -
- 32)) |
- (1u
- << (AArch64::
- QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID -
- 32)) |
- (1u << (AArch64::QQQQRegClassID - 32)) |
- (1u << (AArch64::QQQQ_with_qsub0_in_FPR128_loRegClassID - 32)) |
- (1u << (AArch64::QQQQ_with_qsub1_in_FPR128_loRegClassID - 32)) |
- (1u << (AArch64::QQQQ_with_qsub2_in_FPR128_loRegClassID - 32)) |
- (1u << (AArch64::QQQQ_with_qsub3_in_FPR128_loRegClassID - 32)) |
- (1u
- << (AArch64::
- QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClassID -
- 32)) |
- (1u
- << (AArch64::
- QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID -
- 32)) |
- (1u
- << (AArch64::
- QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID -
- 32)) |
- (1u
- << (AArch64::
- QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID -
- 32)) |
- (1u
- << (AArch64::
- QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID -
- 32)) |
- (1u
- << (AArch64::
- QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID -
- 32)) |
- (1u
- << (AArch64::
- QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loRegClassID -
- 32)) |
- (1u << (AArch64::QQQRegClassID - 32)) |
- (1u << (AArch64::QQQ_with_qsub0_in_FPR128_loRegClassID - 32)) |
- (1u << (AArch64::QQQ_with_qsub1_in_FPR128_loRegClassID - 32)) |
- (1u << (AArch64::QQQ_with_qsub2_in_FPR128_loRegClassID - 32)) |
- (1u
- << (AArch64::
- QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loRegClassID -
- 32)),
- // FIXME: The entries below this point can be safely removed once this
- // is tablegenerated. It's only needed because of the hardcoded register
- // class limit.
- // Classes 64-96
- 0,
- // Classes 97-128
- 0,
- // Classes 129-160
- 0,
- // Classes 161-192
- 0,
- // Classes 193-224
- 0,
-};
-
-const uint32_t CCRCoverageData[] = {
- // Classes 0-31
- 1u << AArch64::CCRRegClassID,
- // Classes 32-63
- 0,
- // FIXME: The entries below this point can be safely removed once this
- // is tablegenerated. It's only needed because of the hardcoded register
- // class limit.
- // Classes 64-96
- 0,
- // Classes 97-128
- 0,
- // Classes 129-160
- 0,
- // Classes 161-192
- 0,
- // Classes 193-224
- 0,
-};
-
-RegisterBank GPRRegBank(AArch64::GPRRegBankID, "GPR", 64, GPRCoverageData);
-RegisterBank FPRRegBank(AArch64::FPRRegBankID, "FPR", 512, FPRCoverageData);
-RegisterBank CCRRegBank(AArch64::CCRRegBankID, "CCR", 32, CCRCoverageData);
-} // end namespace AArch64
-
-RegisterBank *AArch64GenRegisterBankInfo::RegBanks[] = {
- &AArch64::GPRRegBank, &AArch64::FPRRegBank, &AArch64::CCRRegBank};
-
RegisterBankInfo::PartialMapping AArch64GenRegisterBankInfo::PartMappings[]{
/* StartIdx, Length, RegBank */
- // 0: GPR 32-bit value.
- {0, 32, AArch64::GPRRegBank},
- // 1: GPR 64-bit value.
- {0, 64, AArch64::GPRRegBank},
- // 2: FPR 32-bit value.
+ // 0: FPR 32-bit value.
{0, 32, AArch64::FPRRegBank},
- // 3: FPR 64-bit value.
+ // 1: FPR 64-bit value.
{0, 64, AArch64::FPRRegBank},
- // 4: FPR 128-bit value.
+ // 2: FPR 128-bit value.
{0, 128, AArch64::FPRRegBank},
- // 5: FPR 256-bit value.
+ // 3: FPR 256-bit value.
{0, 256, AArch64::FPRRegBank},
- // 6: FPR 512-bit value.
- {0, 512, AArch64::FPRRegBank}};
+ // 4: FPR 512-bit value.
+ {0, 512, AArch64::FPRRegBank},
+ // 5: GPR 32-bit value.
+ {0, 32, AArch64::GPRRegBank},
+ // 6: GPR 64-bit value.
+ {0, 64, AArch64::GPRRegBank},
+};
// ValueMappings.
RegisterBankInfo::ValueMapping AArch64GenRegisterBankInfo::ValMappings[]{
/* BreakDown, NumBreakDowns */
// 3-operands instructions (all binary operations should end up with one of
// those mapping).
- // 0: GPR 32-bit value. <-- This must match First3OpsIdx.
- {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR32 - PMI_Min], 1},
- {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR32 - PMI_Min], 1},
- {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR32 - PMI_Min], 1},
- // 3: GPR 64-bit value.
- {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1},
- {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1},
- {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1},
- // 6: FPR 32-bit value.
+ // 0: FPR 32-bit value. <-- This must match First3OpsIdx.
{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1},
{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1},
{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1},
- // 9: FPR 64-bit value.
+ // 3: FPR 64-bit value.
{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
- // 12: FPR 128-bit value.
+ // 6: FPR 128-bit value.
{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR128 - PMI_Min], 1},
{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR128 - PMI_Min], 1},
{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR128 - PMI_Min], 1},
- // 15: FPR 256-bit value.
+ // 9: FPR 256-bit value.
{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR256 - PMI_Min], 1},
{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR256 - PMI_Min], 1},
{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR256 - PMI_Min], 1},
- // 18: FPR 512-bit value. <-- This must match Last3OpsIdx.
+ // 12: FPR 512-bit value.
{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR512 - PMI_Min], 1},
{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR512 - PMI_Min], 1},
{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR512 - PMI_Min], 1},
+ // 15: GPR 32-bit value.
+ {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR32 - PMI_Min], 1},
+ {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR32 - PMI_Min], 1},
+ {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR32 - PMI_Min], 1},
+ // 18: GPR 64-bit value. <-- This must match Last3OpsIdx.
+ {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1},
+ {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1},
+ {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1},
// Cross register bank copies.
- // 21: GPR 32-bit value to FPR 32-bit value. <-- This must match
+ // 21: FPR 32-bit value to GPR 32-bit value. <-- This must match
// FirstCrossRegCpyIdx.
- {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR32 - PMI_Min], 1},
{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1},
- // 23: GPR 64-bit value to FPR 64-bit value.
- {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1},
+ {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR32 - PMI_Min], 1},
+ // 23: FPR 64-bit value to GPR 64-bit value.
{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
- // 25: FPR 32-bit value to GPR 32-bit value.
- {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1},
+ {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1},
+ // 25: FPR 128-bit value to GPR 128-bit value (invalid)
+ {nullptr, 1},
+ {nullptr, 1},
+ // 27: FPR 256-bit value to GPR 256-bit value (invalid)
+ {nullptr, 1},
+ {nullptr, 1},
+ // 29: FPR 512-bit value to GPR 512-bit value (invalid)
+ {nullptr, 1},
+ {nullptr, 1},
+ // 31: GPR 32-bit value to FPR 32-bit value.
{&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR32 - PMI_Min], 1},
- // 27: FPR 64-bit value to GPR 64-bit value. <-- This must match
+ {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1},
+ // 33: GPR 64-bit value to FPR 64-bit value. <-- This must match
// LastCrossRegCpyIdx.
+ {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1},
{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
- {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1}
};
bool AArch64GenRegisterBankInfo::checkPartialMap(unsigned Idx,
@@ -301,9 +178,9 @@ AArch64GenRegisterBankInfo::getValueMapp
AArch64GenRegisterBankInfo::PartialMappingIdx
AArch64GenRegisterBankInfo::BankIDToCopyMapIdx[]{
- PMI_FirstGPR, // GPR
- PMI_FirstFPR, // FPR
PMI_None, // CCR
+ PMI_FirstFPR, // FPR
+ PMI_FirstGPR, // GPR
};
const RegisterBankInfo::ValueMapping *
Modified: llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp?rev=292478&r1=292477&r2=292478&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp Thu Jan 19 05:15:55 2017
@@ -21,6 +21,9 @@
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
+#define GET_TARGET_REGBANK_IMPL
+#include "AArch64GenRegisterBank.inc"
+
// This file will be TableGen'ed at some point.
#include "AArch64GenRegisterBankInfo.def"
@@ -30,9 +33,6 @@ using namespace llvm;
#error "You shouldn't build this"
#endif
-AArch64GenRegisterBankInfo::AArch64GenRegisterBankInfo()
- : RegisterBankInfo(RegBanks, AArch64::NumRegisterBanks) {}
-
AArch64RegisterBankInfo::AArch64RegisterBankInfo(const TargetRegisterInfo &TRI)
: AArch64GenRegisterBankInfo() {
static bool AlreadyInit = false;
Modified: llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.h?rev=292478&r1=292477&r2=292478&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.h (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.h Thu Jan 19 05:15:55 2017
@@ -16,40 +16,30 @@
#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
+#define GET_REGBANK_DECLARATIONS
+#include "AArch64GenRegisterBank.inc"
+
namespace llvm {
class TargetRegisterInfo;
-namespace AArch64 {
-enum {
- GPRRegBankID = 0, /// General Purpose Registers: W, X.
- FPRRegBankID = 1, /// Floating Point/Vector Registers: B, H, S, D, Q.
- CCRRegBankID = 2, /// Conditional register: NZCV.
- NumRegisterBanks
-};
-} // End AArch64 namespace.
-
class AArch64GenRegisterBankInfo : public RegisterBankInfo {
-private:
- static RegisterBank *RegBanks[];
-
protected:
- AArch64GenRegisterBankInfo();
enum PartialMappingIdx {
PMI_None = -1,
- PMI_GPR32 = 1,
- PMI_GPR64,
- PMI_FPR32,
+ PMI_FPR32 = 1,
PMI_FPR64,
PMI_FPR128,
PMI_FPR256,
PMI_FPR512,
+ PMI_GPR32,
+ PMI_GPR64,
PMI_FirstGPR = PMI_GPR32,
PMI_LastGPR = PMI_GPR64,
PMI_FirstFPR = PMI_FPR32,
PMI_LastFPR = PMI_FPR512,
- PMI_Min = PMI_FirstGPR,
+ PMI_Min = PMI_FirstFPR,
};
static RegisterBankInfo::PartialMapping PartMappings[];
@@ -61,7 +51,7 @@ protected:
Last3OpsIdx = 18,
DistanceBetweenRegBanks = 3,
FirstCrossRegCpyIdx = 21,
- LastCrossRegCpyIdx = 27,
+ LastCrossRegCpyIdx = 33,
DistanceBetweenCrossRegCpy = 2
};
@@ -90,6 +80,9 @@ protected:
/// register bank with a size of \p Size.
static const RegisterBankInfo::ValueMapping *
getCopyMapping(unsigned DstBankID, unsigned SrcBankID, unsigned Size);
+
+#define GET_TARGET_REGBANK_CLASS
+#include "AArch64GenRegisterBank.inc"
};
/// This class provides the information for the target register banks.
Modified: llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.cpp?rev=292478&r1=292477&r2=292478&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.cpp Thu Jan 19 05:15:55 2017
@@ -14,7 +14,9 @@
#include "AArch64CallLowering.h"
#include "AArch64InstructionSelector.h"
#include "AArch64LegalizerInfo.h"
+#ifdef LLVM_BUILD_GLOBAL_ISEL
#include "AArch64RegisterBankInfo.h"
+#endif
#include "AArch64Subtarget.h"
#include "AArch64TargetMachine.h"
#include "AArch64TargetObjectFile.h"
Modified: llvm/trunk/lib/Target/AArch64/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/CMakeLists.txt?rev=292478&r1=292477&r2=292478&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/CMakeLists.txt (original)
+++ llvm/trunk/lib/Target/AArch64/CMakeLists.txt Thu Jan 19 05:15:55 2017
@@ -14,6 +14,7 @@ tablegen(LLVM AArch64GenSubtargetInfo.in
tablegen(LLVM AArch64GenDisassemblerTables.inc -gen-disassembler)
tablegen(LLVM AArch64GenSystemOperands.inc -gen-searchable-tables)
if(LLVM_BUILD_GLOBAL_ISEL)
+ tablegen(LLVM AArch64GenRegisterBank.inc -gen-register-bank)
tablegen(LLVM AArch64GenGlobalISel.inc -gen-global-isel)
endif()
Modified: llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp?rev=292478&r1=292477&r2=292478&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp Thu Jan 19 05:15:55 2017
@@ -55,7 +55,9 @@ const uint32_t GPRCoverageData[] = {
0,
};
-RegisterBank GPRRegBank(ARM::GPRRegBankID, "GPRB", 32, ARM::GPRCoverageData);
+// FIXME: The 200 will be replaced by the number of register classes when this is
+// tablegenerated.
+RegisterBank GPRRegBank(ARM::GPRRegBankID, "GPRB", 32, ARM::GPRCoverageData, 200);
RegisterBank *RegBanks[] = {&GPRRegBank};
RegisterBankInfo::PartialMapping GPRPartialMapping{0, 32, GPRRegBank};
Modified: llvm/trunk/utils/TableGen/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CMakeLists.txt?rev=292478&r1=292477&r2=292478&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/CMakeLists.txt (original)
+++ llvm/trunk/utils/TableGen/CMakeLists.txt Thu Jan 19 05:15:55 2017
@@ -27,6 +27,7 @@ add_tablegen(llvm-tblgen LLVM
IntrinsicEmitter.cpp
OptParserEmitter.cpp
PseudoLoweringEmitter.cpp
+ RegisterBankEmitter.cpp
RegisterInfoEmitter.cpp
SearchableTableEmitter.cpp
SubtargetEmitter.cpp
Copied: llvm/trunk/utils/TableGen/RegisterBankEmitter.cpp (from r292368, llvm/trunk/utils/TableGen/RegisterBankEmitter.cpp)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/RegisterBankEmitter.cpp?p2=llvm/trunk/utils/TableGen/RegisterBankEmitter.cpp&p1=llvm/trunk/utils/TableGen/RegisterBankEmitter.cpp&r1=292368&r2=292478&rev=292478&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/RegisterBankEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/RegisterBankEmitter.cpp Thu Jan 19 05:15:55 2017
@@ -173,7 +173,8 @@ static void visitRegisterBankClasses(
VisitFn(RC, Kind.str());
for (const auto &PossibleSubclass : RegisterClassHierarchy.getRegClasses()) {
- Twine TmpKind = Kind + " (" + PossibleSubclass.getName() + ")";
+ std::string TmpKind =
+ (Twine(Kind) + " (" + PossibleSubclass.getName() + ")").str();
// Visit each subclass of an explicitly named class.
if (RC != &PossibleSubclass && RC->hasSubClass(&PossibleSubclass))
@@ -191,9 +192,10 @@ static void visitRegisterBankClasses(
BitVector BV(RegisterClassHierarchy.getRegClasses().size());
PossibleSubclass.getSuperRegClasses(&SubIdx, BV);
if (BV.test(RC->EnumValue)) {
- Twine TmpKind2 = TmpKind + " " + RC->getName() +
- " class-with-subregs: " + RC->getName();
- VisitFn(&PossibleSubclass, TmpKind2.str());
+ std::string TmpKind2 = (Twine(TmpKind) + " " + RC->getName() +
+ " class-with-subregs: " + RC->getName())
+ .str();
+ VisitFn(&PossibleSubclass, TmpKind2);
}
}
}
@@ -217,8 +219,8 @@ void RegisterBankEmitter::emitBaseClassI
for (const auto &RCs : RCsGroupedByWord) {
OS << " // " << LowestIdxInWord << "-" << (LowestIdxInWord + 31) << "\n";
for (const auto &RC : RCs) {
- Twine QualifiedRegClassID =
- TargetName + "::" + RC->getName() + "RegClassID";
+ std::string QualifiedRegClassID =
+ (Twine(TargetName) + "::" + RC->getName() + "RegClassID").str();
OS << " (1u << (" << QualifiedRegClassID << " - "
<< LowestIdxInWord << ")) |\n";
}
@@ -230,7 +232,8 @@ void RegisterBankEmitter::emitBaseClassI
OS << "\n";
for (const auto &Bank : Banks) {
- Twine QualifiedBankID = TargetName + "::" + Bank.getEnumeratorName();
+ std::string QualifiedBankID =
+ (TargetName + "::" + Bank.getEnumeratorName()).str();
unsigned Size = Bank.getRCWithLargestRegsSize()->SpillSize;
OS << "RegisterBank " << Bank.getInstanceVarName() << "(/* ID */ "
<< QualifiedBankID << ", /* Name */ \"" << Bank.getName()
Modified: llvm/trunk/utils/TableGen/TableGen.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/TableGen.cpp?rev=292478&r1=292477&r2=292478&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/TableGen.cpp (original)
+++ llvm/trunk/utils/TableGen/TableGen.cpp Thu Jan 19 05:15:55 2017
@@ -46,6 +46,7 @@ enum ActionType {
GenAttributes,
GenSearchableTables,
GenGlobalISel,
+ GenRegisterBank,
};
namespace {
@@ -94,7 +95,9 @@ namespace {
clEnumValN(GenSearchableTables, "gen-searchable-tables",
"Generate generic binary-searchable table"),
clEnumValN(GenGlobalISel, "gen-global-isel",
- "Generate GlobalISel selector")));
+ "Generate GlobalISel selector"),
+ clEnumValN(GenRegisterBank, "gen-register-bank",
+ "Generate registers bank descriptions")));
cl::opt<std::string>
Class("class", cl::desc("Print Enum list for this class"),
@@ -182,6 +185,8 @@ bool LLVMTableGenMain(raw_ostream &OS, R
break;
case GenGlobalISel:
EmitGlobalISel(Records, OS);
+ case GenRegisterBank:
+ EmitRegisterBank(Records, OS);
break;
}
Modified: llvm/trunk/utils/TableGen/TableGenBackends.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/TableGenBackends.h?rev=292478&r1=292477&r2=292478&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/TableGenBackends.h (original)
+++ llvm/trunk/utils/TableGen/TableGenBackends.h Thu Jan 19 05:15:55 2017
@@ -81,6 +81,7 @@ void EmitCTags(RecordKeeper &RK, raw_ost
void EmitAttributes(RecordKeeper &RK, raw_ostream &OS);
void EmitSearchableTables(RecordKeeper &RK, raw_ostream &OS);
void EmitGlobalISel(RecordKeeper &RK, raw_ostream &OS);
+void EmitRegisterBank(RecordKeeper &RK, raw_ostream &OS);
} // End llvm namespace
More information about the llvm-commits
mailing list