[llvm] r292476 - GlobalISel: Implement widening for shifts

[Justin Bogner via llvm-commits]

Author: bogner
Date: Thu Jan 19 01:51:17 2017
New Revision: 292476

URL: http://llvm.org/viewvc/llvm-project?rev=292476&view=rev
Log:
GlobalISel: Implement widening for shifts

Added:
    llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir
Modified:
    llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

Modified: llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp?rev=292476&r1=292475&r2=292476&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp (original)
+++ llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp Thu Jan 19 01:51:17 2017
@@ -222,7 +222,8 @@ LegalizerHelper::widenScalar(MachineInst
   case TargetOpcode::G_MUL:
   case TargetOpcode::G_OR:
   case TargetOpcode::G_XOR:
-  case TargetOpcode::G_SUB: {
+  case TargetOpcode::G_SUB:
+  case TargetOpcode::G_SHL: {
     // Perform operation at larger width (any extension is fine here, high bits
     // don't affect the result) and then truncate the result back to the
     // original type.
@@ -242,10 +243,13 @@ LegalizerHelper::widenScalar(MachineInst
     return Legalized;
   }
   case TargetOpcode::G_SDIV:
-  case TargetOpcode::G_UDIV: {
-    unsigned ExtOp = MI.getOpcode() == TargetOpcode::G_SDIV
-                          ? TargetOpcode::G_SEXT
-                          : TargetOpcode::G_ZEXT;
+  case TargetOpcode::G_UDIV:
+  case TargetOpcode::G_ASHR:
+  case TargetOpcode::G_LSHR: {
+    unsigned ExtOp = MI.getOpcode() == TargetOpcode::G_SDIV ||
+                             MI.getOpcode() == TargetOpcode::G_ASHR
+                         ? TargetOpcode::G_SEXT
+                         : TargetOpcode::G_ZEXT;
 
     unsigned LHSExt = MRI.createGenericVirtualRegister(WideTy);
     MIRBuilder.buildInstr(ExtOp).addDef(LHSExt).addUse(

Added: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir?rev=292476&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir (added)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir Thu Jan 19 01:51:17 2017
@@ -0,0 +1,44 @@
+# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - 2>&1 | FileCheck %s
+
+--- |
+  target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
+  target triple = "aarch64--"
+  define void @test_shift() {
+  entry:
+    ret void
+  }
+...
+
+---
+name:            test_shift
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: _ }
+  - { id: 4, class: _ }
+  - { id: 5, class: _ }
+  - { id: 6, class: _ }
+body: |
+  bb.0.entry:
+    liveins: %x0, %x1, %x2, %x3
+    %0(s64) = COPY %x0
+    %1(s64) = COPY %x1
+    %2(s8) = G_TRUNC %0
+    %3(s8) = G_TRUNC %1
+
+    ; CHECK: [[LHS32:%[0-9]+]](s32) = G_SEXT %2
+    ; CHECK: [[RHS32:%[0-9]+]](s32) = G_SEXT %3
+    ; CHECK: [[RES32:%[0-9]+]](s32) = G_ASHR [[LHS32]], [[RHS32]]
+    ; CHECK: %4(s8) = G_TRUNC [[RES32]]
+    %4(s8) = G_ASHR %2, %3
+
+    ; CHECK: [[LHS32:%[0-9]+]](s32) = G_ZEXT %2
+    ; CHECK: [[RHS32:%[0-9]+]](s32) = G_ZEXT %3
+    ; CHECK: [[RES32:%[0-9]+]](s32) = G_LSHR [[LHS32]], [[RHS32]]
+    ; CHECK: %5(s8) = G_TRUNC [[RES32]]
+    %5(s8) = G_LSHR %2, %3
+
+    ; CHECK: %6(s8) = G_SHL %2, %3
+    %6(s8) = G_SHL %2, %3
+...