[PATCH] D28805: [GlobalISel] Pointers are legal operands for G_SELECT on AArch64

[Kristof Beyls via Phabricator via llvm-commits]

kristof.beyls created this revision.
Herald added subscribers: dberris, rengolin, aemerson.

This makes another 13 tests pass in the test-suite for me.

I'm not sure if we could tablegen the functionality I'm touching in this patch.
Even if we did, I think that manually fixing this is helpful, as it results in other issues being hidden less while we don't have tablegen for this.


https://reviews.llvm.org/D28805

Files:
  lib/Target/AArch64/AArch64InstructionSelector.cpp
  lib/Target/AArch64/AArch64LegalizerInfo.cpp
  test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir


Index: test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir
===================================================================
--- test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir
+++ test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir
@@ -2973,20 +2973,28 @@
 # CHECK-NEXT:  - { id: 4, class: gpr64 }
 # CHECK-NEXT:  - { id: 5, class: gpr64 }
 # CHECK-NEXT:  - { id: 6, class: gpr64 }
+# CHECK-NEXT:  - { id: 7, class: gpr64 }
+# CHECK-NEXT:  - { id: 8, class: gpr64 }
+# CHECK-NEXT:  - { id: 9, class: gpr64 }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
   - { id: 4, class: gpr }
   - { id: 5, class: gpr }
   - { id: 6, class: gpr }
+  - { id: 7, class: gpr }
+  - { id: 8, class: gpr }
+  - { id: 9, class: gpr }
 
 # CHECK:  body:
 # CHECK:      %wzr = ANDSWri %0, 0, implicit-def %nzcv
 # CHECK:      %3 = CSELWr %1, %2, 1, implicit %nzcv
 # CHECK:      %wzr = ANDSWri %0, 0, implicit-def %nzcv
 # CHECK:      %6 = CSELXr %4, %5, 1, implicit %nzcv
+# CHECK:      %wzr = ANDSWri %0, 0, implicit-def %nzcv
+# CHECK:      %9 = CSELXr %7, %8, 1, implicit %nzcv
 body:             |
   bb.0:
     liveins: %w0, %w1, %w2
@@ -2999,4 +3007,8 @@
     %4(s64) = COPY %x0
     %5(s64) = COPY %x1
     %6(s64) = G_SELECT %0, %4, %5
+
+    %7(p0) = COPY %x0
+    %8(p0) = COPY %x1
+    %9(p0) = G_SELECT %0, %7, %8
 ...
Index: lib/Target/AArch64/AArch64LegalizerInfo.cpp
===================================================================
--- lib/Target/AArch64/AArch64LegalizerInfo.cpp
+++ lib/Target/AArch64/AArch64LegalizerInfo.cpp
@@ -161,7 +161,7 @@
   setAction({G_BRINDIRECT, p0}, Legal);
 
   // Select
-  for (auto Ty : {s1, s8, s16, s32, s64})
+  for (auto Ty : {s1, s8, s16, s32, s64, p0})
     setAction({G_SELECT, Ty}, Legal);
 
   setAction({G_SELECT, 1, s1}, Legal);
Index: lib/Target/AArch64/AArch64InstructionSelector.cpp
===================================================================
--- lib/Target/AArch64/AArch64InstructionSelector.cpp
+++ lib/Target/AArch64/AArch64InstructionSelector.cpp
@@ -1031,7 +1031,7 @@
 
     if (Ty == LLT::scalar(32)) {
       CSelOpc = AArch64::CSELWr;
-    } else if (Ty == LLT::scalar(64)) {
+    } else if (Ty == LLT::scalar(64) || Ty == LLT::pointer(0, 64)) {
       CSelOpc = AArch64::CSELXr;
     } else {
       return false;


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