[PATCH] D28720: [NVPTX] Add lowering for llvm.bitreverse.

[Justin Lebar via Phabricator via llvm-commits]

jlebar created this revision.
jlebar added a reviewer: tra.
jlebar added a subscriber: llvm-commits.
Herald added a subscriber: jholewinski.

https://reviews.llvm.org/D28720

Files:
  llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
  llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
  llvm/test/CodeGen/NVPTX/intrinsics.ll


Index: llvm/test/CodeGen/NVPTX/intrinsics.ll
===================================================================
--- llvm/test/CodeGen/NVPTX/intrinsics.ll
+++ llvm/test/CodeGen/NVPTX/intrinsics.ll
@@ -22,6 +22,22 @@
   ret float %val
 }
 
+; CHECK-LABEL: test_bitreverse32(
+define i32 @test_bitreverse32(i32 %a) {
+; CHECK: brev.b32
+  %val = call i32 @llvm.bitreverse.i32(i32 %a)
+  ret i32 %val
+}
+
+; CHECK-LABEL: test_bitreverse64(
+define i64 @test_bitreverse64(i64 %a) {
+; CHECK: brev.b64
+  %val = call i64 @llvm.bitreverse.i64(i64 %a)
+  ret i64 %val
+}
+
 declare float @llvm.fabs.f32(float)
 declare double @llvm.fabs.f64(double)
 declare float @llvm.nvvm.sqrt.f(float)
+declare i32 @llvm.bitreverse.i32(i32)
+declare i64 @llvm.bitreverse.i64(i64)
Index: llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
===================================================================
--- llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
+++ llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
@@ -1090,6 +1090,16 @@
 defm SRA : SHIFT<"shr.s", sra>;
 defm SRL : SHIFT<"shr.u", srl>;
 
+// Bit-reverse
+def BREV32 :
+  NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$a),
+             "brev.b32 \t$dst, $a",
+             [(set Int32Regs:$dst, (bitreverse Int32Regs:$a))]>;
+def BREV64 :
+  NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$a),
+             "brev.b64 \t$dst, $a",
+             [(set Int64Regs:$dst, (bitreverse Int64Regs:$a))]>;
+
 //
 // Rotate: Use ptx shf instruction if available.
 //
Index: llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
===================================================================
--- llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
+++ llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
@@ -195,6 +195,9 @@
   setOperationAction(ISD::SRA_PARTS, MVT::i64  , Custom);
   setOperationAction(ISD::SRL_PARTS, MVT::i64  , Custom);
 
+  setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
+  setOperationAction(ISD::BITREVERSE, MVT::i64, Legal);
+
   if (STI.hasROT64()) {
     setOperationAction(ISD::ROTL, MVT::i64, Legal);
     setOperationAction(ISD::ROTR, MVT::i64, Legal);


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