[llvm] r291934 - [InstCombine] use m_APInt to allow shl folds for vectors with splat constants
Sanjay Patel via llvm-commits
llvm-commits at lists.llvm.org
Fri Jan 13 10:39:09 PST 2017
Author: spatel
Date: Fri Jan 13 12:39:09 2017
New Revision: 291934
URL: http://llvm.org/viewvc/llvm-project?rev=291934&view=rev
Log:
[InstCombine] use m_APInt to allow shl folds for vectors with splat constants
Modified:
llvm/trunk/lib/Transforms/InstCombine/InstCombineShifts.cpp
llvm/trunk/test/Transforms/InstCombine/shift.ll
Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineShifts.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineShifts.cpp?rev=291934&r1=291933&r2=291934&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/InstCombine/InstCombineShifts.cpp (original)
+++ llvm/trunk/lib/Transforms/InstCombine/InstCombineShifts.cpp Fri Jan 13 12:39:09 2017
@@ -723,8 +723,9 @@ Instruction *InstCombiner::visitShl(Bina
if (Instruction *V = commonShiftTransforms(I))
return V;
- if (ConstantInt *Op1C = dyn_cast<ConstantInt>(Op1)) {
- unsigned ShAmt = Op1C->getZExtValue();
+ const APInt *ShAmtAPInt;
+ if (match(Op1, m_APInt(ShAmtAPInt))) {
+ unsigned ShAmt = ShAmtAPInt->getZExtValue();
// Turn:
// %zext = zext i32 %V to i64
@@ -748,7 +749,8 @@ Instruction *InstCombiner::visitShl(Bina
// If the shifted-out value is known-zero, then this is a NUW shift.
if (!I.hasNoUnsignedWrap() &&
MaskedValueIsZero(
- Op0, APInt::getHighBitsSet(Op1C->getBitWidth(), ShAmt), 0, &I)) {
+ Op0, APInt::getHighBitsSet(ShAmtAPInt->getBitWidth(), ShAmt), 0,
+ &I)) {
I.setHasNoUnsignedWrap();
return &I;
}
Modified: llvm/trunk/test/Transforms/InstCombine/shift.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/shift.ll?rev=291934&r1=291933&r2=291934&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/shift.ll (original)
+++ llvm/trunk/test/Transforms/InstCombine/shift.ll Fri Jan 13 12:39:09 2017
@@ -455,7 +455,7 @@ define i32 @test25(i32 %tmp.2, i32 %AA)
define <2 x i32> @test25_vector(<2 x i32> %tmp.2, <2 x i32> %AA) {
; CHECK-LABEL: @test25_vector(
; CHECK-NEXT: [[TMP_3:%.*]] = lshr <2 x i32> %tmp.2, <i32 17, i32 17>
-; CHECK-NEXT: [[TMP_51:%.*]] = shl <2 x i32> [[TMP_3]], <i32 17, i32 17>
+; CHECK-NEXT: [[TMP_51:%.*]] = shl nuw <2 x i32> [[TMP_3]], <i32 17, i32 17>
; CHECK-NEXT: [[X2:%.*]] = add <2 x i32> [[TMP_51]], %AA
; CHECK-NEXT: [[TMP_6:%.*]] = and <2 x i32> [[X2]], <i32 -131072, i32 -131072>
; CHECK-NEXT: ret <2 x i32> [[TMP_6]]
@@ -671,7 +671,7 @@ define i64 @test37(i128 %A, i32 %B) {
define <2 x i32> @shl_nuw_nsw_splat_vec(<2 x i8> %x) {
; CHECK-LABEL: @shl_nuw_nsw_splat_vec(
; CHECK-NEXT: [[T2:%.*]] = zext <2 x i8> %x to <2 x i32>
-; CHECK-NEXT: [[T3:%.*]] = shl <2 x i32> [[T2]], <i32 17, i32 17>
+; CHECK-NEXT: [[T3:%.*]] = shl nuw nsw <2 x i32> [[T2]], <i32 17, i32 17>
; CHECK-NEXT: ret <2 x i32> [[T3]]
;
%t2 = zext <2 x i8> %x to <2 x i32>
@@ -1070,8 +1070,8 @@ define i64 @test_64(i32 %t) {
define <2 x i64> @test_64_splat_vec(<2 x i32> %t) {
; CHECK-LABEL: @test_64_splat_vec(
; CHECK-NEXT: [[AND:%.*]] = and <2 x i32> %t, <i32 16777215, i32 16777215>
-; CHECK-NEXT: [[EXT:%.*]] = zext <2 x i32> [[AND]] to <2 x i64>
-; CHECK-NEXT: [[SHL:%.*]] = shl <2 x i64> [[EXT]], <i64 8, i64 8>
+; CHECK-NEXT: [[TMP1:%.*]] = shl nuw <2 x i32> [[AND]], <i32 8, i32 8>
+; CHECK-NEXT: [[SHL:%.*]] = zext <2 x i32> [[TMP1]] to <2 x i64>
; CHECK-NEXT: ret <2 x i64> [[SHL]]
;
%and = and <2 x i32> %t, <i32 16777215, i32 16777215>
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