[llvm] r291926 - [InstCombine] add tests to show missing transforms for vector shl; NFC

[Sanjay Patel via llvm-commits]

Author: spatel
Date: Fri Jan 13 12:27:23 2017
New Revision: 291926

URL: http://llvm.org/viewvc/llvm-project?rev=291926&view=rev
Log:
[InstCombine] add tests to show missing transforms for vector shl; NFC

Modified:
    llvm/trunk/test/Transforms/InstCombine/shift.ll

Modified: llvm/trunk/test/Transforms/InstCombine/shift.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/shift.ll?rev=291926&r1=291925&r2=291926&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/shift.ll (original)
+++ llvm/trunk/test/Transforms/InstCombine/shift.ll Fri Jan 13 12:27:23 2017
@@ -640,30 +640,25 @@ define <2 x i1> @test35vec(<2 x i32> %X)
 
 define i128 @test36(i128 %A, i128 %B) {
 ; CHECK-LABEL: @test36(
-; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP231:%.*]] = or i128 %B, %A
 ; CHECK-NEXT:    [[INS:%.*]] = and i128 [[TMP231]], 18446744073709551615
 ; CHECK-NEXT:    ret i128 [[INS]]
 ;
-entry:
   %tmp27 = shl i128 %A, 64
   %tmp23 = shl i128 %B, 64
   %ins = or i128 %tmp23, %tmp27
   %tmp45 = lshr i128 %ins, 64
   ret i128 %tmp45
-
 }
 
 define i64 @test37(i128 %A, i32 %B) {
 ; CHECK-LABEL: @test37(
-; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP22:%.*]] = zext i32 %B to i128
 ; CHECK-NEXT:    [[TMP23:%.*]] = shl nuw nsw i128 [[TMP22]], 32
 ; CHECK-NEXT:    [[INS:%.*]] = or i128 [[TMP23]], %A
 ; CHECK-NEXT:    [[TMP46:%.*]] = trunc i128 [[INS]] to i64
 ; CHECK-NEXT:    ret i64 [[TMP46]]
 ;
-entry:
   %tmp27 = shl i128 %A, 64
   %tmp22 = zext i32 %B to i128
   %tmp23 = shl i128 %tmp22, 96
@@ -671,7 +666,17 @@ entry:
   %tmp45 = lshr i128 %ins, 64
   %tmp46 = trunc i128 %tmp45 to i64
   ret i64 %tmp46
+}
 
+define <2 x i32> @shl_nuw_nsw_splat_vec(<2 x i8> %x) {
+; CHECK-LABEL: @shl_nuw_nsw_splat_vec(
+; CHECK-NEXT:    [[T2:%.*]] = zext <2 x i8> %x to <2 x i32>
+; CHECK-NEXT:    [[T3:%.*]] = shl <2 x i32> [[T2]], <i32 17, i32 17>
+; CHECK-NEXT:    ret <2 x i32> [[T3]]
+;
+  %t2 = zext <2 x i8> %x to <2 x i32>
+  %t3 = shl <2 x i32> %t2, <i32 17, i32 17>
+  ret <2 x i32> %t3
 }
 
 define i32 @test38(i32 %x) nounwind readnone {
@@ -1061,3 +1066,17 @@ define i64 @test_64(i32 %t) {
   %shl = shl i64 %ext, 8
   ret i64 %shl
 }
+
+define <2 x i64> @test_64_splat_vec(<2 x i32> %t) {
+; CHECK-LABEL: @test_64_splat_vec(
+; CHECK-NEXT:    [[AND:%.*]] = and <2 x i32> %t, <i32 16777215, i32 16777215>
+; CHECK-NEXT:    [[EXT:%.*]] = zext <2 x i32> [[AND]] to <2 x i64>
+; CHECK-NEXT:    [[SHL:%.*]] = shl <2 x i64> [[EXT]], <i64 8, i64 8>
+; CHECK-NEXT:    ret <2 x i64> [[SHL]]
+;
+  %and = and <2 x i32> %t, <i32 16777215, i32 16777215>
+  %ext = zext <2 x i32> %and to <2 x i64>
+  %shl = shl <2 x i64> %ext, <i64 8, i64 8>
+  ret <2 x i64> %shl
+}
+