[PATCH] D28152: Cortex-A57 scheduling model for ARM backend (AArch32)

[Andrew Zhogin via Phabricator via llvm-commits]

andrew.zhogin marked 3 inline comments as done.
andrew.zhogin added inline comments.


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Comment at: lib/Target/ARM/ARMScheduleA57.td:29
+
+// Cortex A57 rev. r1p0 or later
+def IsR1P0AndLaterPred : SchedPredicate<[{!STI->isA57r0px()}]>;
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andrew.zhogin wrote:
> rovka wrote:
> > Could you break this off into a separate patch? I.e. write an initial patch as if everything were r1p0 or later, and another patch with the r0px delta (or the other way around if it's more convenient for you).
> Sure, I will.
IsR1P0AndLaterPred is always false for now, run-time option removed.


https://reviews.llvm.org/D28152