[llvm] r291900 - [aarch64][globalisel] Move getValueMapping/getCopyMapping to AArch64GenRegisterBankInfo. NFC.
Daniel Sanders via llvm-commits
llvm-commits at lists.llvm.org
Fri Jan 13 03:50:35 PST 2017
Author: dsanders
Date: Fri Jan 13 05:50:34 2017
New Revision: 291900
URL: http://llvm.org/viewvc/llvm-project?rev=291900&view=rev
Log:
[aarch64][globalisel] Move getValueMapping/getCopyMapping to AArch64GenRegisterBankInfo. NFC.
Summary:
We did lose a little specificity in the assertion messages for the
PartialMappingIdx enumerators in this change but this was necessary to
avoid unnecessary use of 'public:' and we haven't lost anything that
can't be discovered easily in lldb. Once this is tablegen-erated we could
also safely remove the assertions.
Depends on D27976
Reviewers: t.p.northover, ab, rovka, qcolombet
Subscribers: aditya_nandakumar, aemerson, rengolin, vkalintiris, dberris, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D27978
Modified:
llvm/trunk/lib/Target/AArch64/AArch64GenRegisterBankInfo.def
llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.h
Modified: llvm/trunk/lib/Target/AArch64/AArch64GenRegisterBankInfo.def
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64GenRegisterBankInfo.def?rev=291900&r1=291899&r2=291900&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64GenRegisterBankInfo.def (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64GenRegisterBankInfo.def Fri Jan 13 05:50:34 2017
@@ -216,61 +216,6 @@ RegisterBankInfo::ValueMapping AArch64Ge
{&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1}
};
-namespace AArch64 {
-/// Get the pointer to the ValueMapping representing the RegisterBank
-/// at \p RBIdx with a size of \p Size.
-///
-/// The returned mapping works for instructions with the same kind of
-/// operands for up to 3 operands.
-///
-/// \pre \p RBIdx != PartialMappingIdx::None
-const RegisterBankInfo::ValueMapping *
-getValueMapping(AArch64GenRegisterBankInfo::PartialMappingIdx RBIdx,
- unsigned Size) {
- assert(RBIdx != AArch64GenRegisterBankInfo::PartialMappingIdx::PMI_None &&
- "No mapping needed for that");
- unsigned ValMappingIdx =
- AArch64GenRegisterBankInfo::First3OpsIdx +
- (RBIdx - AArch64GenRegisterBankInfo::PartialMappingIdx::PMI_Min +
- AArch64GenRegisterBankInfo::getRegBankBaseIdxOffset(RBIdx, Size)) *
- AArch64GenRegisterBankInfo::ValueMappingIdx::DistanceBetweenRegBanks;
- assert(ValMappingIdx >= AArch64GenRegisterBankInfo::First3OpsIdx &&
- ValMappingIdx <= AArch64GenRegisterBankInfo::Last3OpsIdx &&
- "Mapping out of bound");
-
- return &AArch64GenRegisterBankInfo::ValMappings[ValMappingIdx];
-}
-
-/// Get the pointer to the ValueMapping of the operands of a copy
-/// instruction from a GPR or FPR register to a GPR or FPR register
-/// with a size of \p Size.
-///
-/// If \p DstIsGPR is true, the destination of the copy is on GPR,
-/// otherwise it is on FPR. Same thing for \p SrcIsGPR.
-const RegisterBankInfo::ValueMapping *
-getCopyMapping(bool DstIsGPR, bool SrcIsGPR, unsigned Size) {
- AArch64GenRegisterBankInfo::PartialMappingIdx DstRBIdx =
- DstIsGPR ? AArch64GenRegisterBankInfo::PMI_FirstGPR
- : AArch64GenRegisterBankInfo::PMI_FirstFPR;
- AArch64GenRegisterBankInfo::PartialMappingIdx SrcRBIdx =
- SrcIsGPR ? AArch64GenRegisterBankInfo::PMI_FirstGPR
- : AArch64GenRegisterBankInfo::PMI_FirstFPR;
- if (DstRBIdx == SrcRBIdx)
- return getValueMapping(DstRBIdx, Size);
- assert(Size <= 64 && "GPR cannot handle that size");
- unsigned ValMappingIdx =
- AArch64GenRegisterBankInfo::FirstCrossRegCpyIdx +
- (DstRBIdx - AArch64GenRegisterBankInfo::PMI_Min +
- AArch64GenRegisterBankInfo::getRegBankBaseIdxOffset(DstRBIdx, Size)) *
- AArch64GenRegisterBankInfo::ValueMappingIdx::
- DistanceBetweenCrossRegCpy;
- assert(ValMappingIdx >= AArch64GenRegisterBankInfo::FirstCrossRegCpyIdx &&
- ValMappingIdx <= AArch64GenRegisterBankInfo::LastCrossRegCpyIdx &&
- "Mapping out of bound");
- return &AArch64GenRegisterBankInfo::ValMappings[ValMappingIdx];
-}
-} // End AArch64 namespace.
-
bool AArch64GenRegisterBankInfo::checkPartialMap(unsigned Idx,
unsigned ValStartIdx,
unsigned ValLength,
@@ -286,9 +231,88 @@ bool AArch64GenRegisterBankInfo::checkVa
unsigned Offset) {
unsigned PartialMapBaseIdx = Idx - PartialMappingIdx::PMI_Min;
const ValueMapping &Map =
- AArch64::getValueMapping((PartialMappingIdx)FirstInBank, Size)[Offset];
+ AArch64GenRegisterBankInfo::getValueMapping((PartialMappingIdx)FirstInBank, Size)[Offset];
return Map.BreakDown == &PartMappings[PartialMapBaseIdx] &&
Map.NumBreakDowns == 1;
}
+bool AArch64GenRegisterBankInfo::checkPartialMappingIdx(
+ PartialMappingIdx FirstAlias, PartialMappingIdx LastAlias,
+ ArrayRef<PartialMappingIdx> Order) {
+ if (Order.front() != FirstAlias)
+ return false;
+ if (Order.back() != LastAlias)
+ return false;
+ if (Order.front() > Order.back())
+ return false;
+
+ PartialMappingIdx Previous = Order.front();
+ bool First = true;
+ for (const auto &Current : Order) {
+ if (First) {
+ First = false;
+ continue;
+ }
+ if (Previous + 1 != Current)
+ return false;
+ Previous = Current;
+ }
+ return true;
+}
+
+unsigned AArch64GenRegisterBankInfo::getRegBankBaseIdxOffset(unsigned RBIdx,
+ unsigned Size) {
+ if (RBIdx == PMI_FirstGPR) {
+ if (Size <= 32)
+ return 0;
+ if (Size <= 64)
+ return 1;
+ llvm_unreachable("Unexpected size");
+ }
+ if (RBIdx == PMI_FirstFPR) {
+ if (Size <= 32)
+ return 0;
+ if (Size <= 64)
+ return 1;
+ if (Size <= 128)
+ return 2;
+ if (Size <= 256)
+ return 3;
+ if (Size <= 512)
+ return 4;
+ llvm_unreachable("Unexpected size");
+ }
+ llvm_unreachable("Unexpected bank");
+}
+
+const RegisterBankInfo::ValueMapping *
+AArch64GenRegisterBankInfo::getValueMapping(PartialMappingIdx RBIdx,
+ unsigned Size) {
+ assert(RBIdx != PartialMappingIdx::PMI_None && "No mapping needed for that");
+ unsigned ValMappingIdx = First3OpsIdx +
+ (RBIdx - PartialMappingIdx::PMI_Min +
+ getRegBankBaseIdxOffset(RBIdx, Size)) *
+ ValueMappingIdx::DistanceBetweenRegBanks;
+ assert(ValMappingIdx >= First3OpsIdx && ValMappingIdx <= Last3OpsIdx &&
+ "Mapping out of bound");
+
+ return &ValMappings[ValMappingIdx];
+}
+
+const RegisterBankInfo::ValueMapping *
+AArch64GenRegisterBankInfo::getCopyMapping(bool DstIsGPR, bool SrcIsGPR,
+ unsigned Size) {
+ PartialMappingIdx DstRBIdx = DstIsGPR ? PMI_FirstGPR : PMI_FirstFPR;
+ PartialMappingIdx SrcRBIdx = SrcIsGPR ? PMI_FirstGPR : PMI_FirstFPR;
+ if (DstRBIdx == SrcRBIdx)
+ return getValueMapping(DstRBIdx, Size);
+ assert(Size <= 64 && "GPR cannot handle that size");
+ unsigned ValMappingIdx =
+ FirstCrossRegCpyIdx +
+ (DstRBIdx - PMI_Min + getRegBankBaseIdxOffset(DstRBIdx, Size)) *
+ ValueMappingIdx::DistanceBetweenCrossRegCpy;
+ assert(ValMappingIdx >= FirstCrossRegCpyIdx &&
+ ValMappingIdx <= LastCrossRegCpyIdx && "Mapping out of bound");
+ return &ValMappings[ValMappingIdx];
+}
} // End llvm namespace.
Modified: llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp?rev=291900&r1=291899&r2=291900&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp Fri Jan 13 05:50:34 2017
@@ -148,8 +148,8 @@ AArch64RegisterBankInfo::AArch64Register
(void)PartialMapDstIdx; \
(void)PartialMapSrcIdx; \
const ValueMapping *Map = \
- AArch64::getCopyMapping(PMI_First##RBNameDst == PMI_FirstGPR, \
- PMI_First##RBNameSrc == PMI_FirstGPR, Size); \
+ getCopyMapping(PMI_First##RBNameDst == PMI_FirstGPR, \
+ PMI_First##RBNameSrc == PMI_FirstGPR, Size); \
(void)Map; \
assert(Map[0].BreakDown == \
&AArch64GenRegisterBankInfo::PartMappings[PartialMapDstIdx] && \
@@ -254,10 +254,10 @@ AArch64RegisterBankInfo::getInstrAlterna
break;
InstructionMappings AltMappings;
InstructionMapping GPRMapping(
- /*ID*/ 1, /*Cost*/ 1, AArch64::getValueMapping(PMI_FirstGPR, Size),
+ /*ID*/ 1, /*Cost*/ 1, getValueMapping(PMI_FirstGPR, Size),
/*NumOperands*/ 3);
InstructionMapping FPRMapping(
- /*ID*/ 2, /*Cost*/ 1, AArch64::getValueMapping(PMI_FirstFPR, Size),
+ /*ID*/ 2, /*Cost*/ 1, getValueMapping(PMI_FirstFPR, Size),
/*NumOperands*/ 3);
AltMappings.emplace_back(std::move(GPRMapping));
@@ -277,21 +277,21 @@ AArch64RegisterBankInfo::getInstrAlterna
InstructionMappings AltMappings;
InstructionMapping GPRMapping(
/*ID*/ 1, /*Cost*/ 1,
- AArch64::getCopyMapping(/*DstIsGPR*/ true, /*SrcIsGPR*/ true, Size),
+ getCopyMapping(/*DstIsGPR*/ true, /*SrcIsGPR*/ true, Size),
/*NumOperands*/ 2);
InstructionMapping FPRMapping(
/*ID*/ 2, /*Cost*/ 1,
- AArch64::getCopyMapping(/*DstIsGPR*/ false, /*SrcIsGPR*/ false, Size),
+ getCopyMapping(/*DstIsGPR*/ false, /*SrcIsGPR*/ false, Size),
/*NumOperands*/ 2);
InstructionMapping GPRToFPRMapping(
/*ID*/ 3,
/*Cost*/ copyCost(AArch64::GPRRegBank, AArch64::FPRRegBank, Size),
- AArch64::getCopyMapping(/*DstIsGPR*/ false, /*SrcIsGPR*/ true, Size),
+ getCopyMapping(/*DstIsGPR*/ false, /*SrcIsGPR*/ true, Size),
/*NumOperands*/ 2);
InstructionMapping FPRToGPRMapping(
/*ID*/ 3,
/*Cost*/ copyCost(AArch64::GPRRegBank, AArch64::FPRRegBank, Size),
- AArch64::getCopyMapping(/*DstIsGPR*/ true, /*SrcIsGPR*/ false, Size),
+ getCopyMapping(/*DstIsGPR*/ true, /*SrcIsGPR*/ false, Size),
/*NumOperands*/ 2);
AltMappings.emplace_back(std::move(GPRMapping));
@@ -313,15 +313,15 @@ AArch64RegisterBankInfo::getInstrAlterna
InstructionMappings AltMappings;
InstructionMapping GPRMapping(
/*ID*/ 1, /*Cost*/ 1,
- getOperandsMapping({AArch64::getValueMapping(PMI_FirstGPR, Size),
+ getOperandsMapping({getValueMapping(PMI_FirstGPR, Size),
// Addresses are GPR 64-bit.
- AArch64::getValueMapping(PMI_FirstGPR, 64)}),
+ getValueMapping(PMI_FirstGPR, 64)}),
/*NumOperands*/ 2);
InstructionMapping FPRMapping(
/*ID*/ 2, /*Cost*/ 1,
- getOperandsMapping({AArch64::getValueMapping(PMI_FirstFPR, Size),
+ getOperandsMapping({getValueMapping(PMI_FirstFPR, Size),
// Addresses are GPR 64-bit.
- AArch64::getValueMapping(PMI_FirstGPR, 64)}),
+ getValueMapping(PMI_FirstGPR, 64)}),
/*NumOperands*/ 2);
AltMappings.emplace_back(std::move(GPRMapping));
@@ -405,8 +405,8 @@ AArch64RegisterBankInfo::getSameKindOfOp
}
#endif // End NDEBUG.
- return InstructionMapping{DefaultMappingID, 1,
- AArch64::getValueMapping(RBIdx, Size), NumOperands};
+ return InstructionMapping{DefaultMappingID, 1, getValueMapping(RBIdx, Size),
+ NumOperands};
}
RegisterBankInfo::InstructionMapping
@@ -457,7 +457,7 @@ AArch64RegisterBankInfo::getInstrMapping
const RegisterBank &SrcRB =
SrcIsGPR ? AArch64::GPRRegBank : AArch64::FPRRegBank;
return InstructionMapping{DefaultMappingID, copyCost(DstRB, SrcRB, Size),
- AArch64::getCopyMapping(DstIsGPR, SrcIsGPR, Size),
+ getCopyMapping(DstIsGPR, SrcIsGPR, Size),
/*NumOperands*/ 2};
}
case TargetOpcode::G_SEQUENCE:
@@ -535,8 +535,7 @@ AArch64RegisterBankInfo::getInstrMapping
SmallVector<const ValueMapping *, 8> OpdsMapping(NumOperands);
for (unsigned Idx = 0; Idx < NumOperands; ++Idx)
if (MI.getOperand(Idx).isReg())
- OpdsMapping[Idx] =
- AArch64::getValueMapping(OpRegBankIdx[Idx], OpSize[Idx]);
+ OpdsMapping[Idx] = getValueMapping(OpRegBankIdx[Idx], OpSize[Idx]);
Mapping.setOperandsMapping(getOperandsMapping(OpdsMapping));
return Mapping;
Modified: llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.h?rev=291900&r1=291899&r2=291900&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.h (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.h Fri Jan 13 05:50:34 2017
@@ -70,51 +70,28 @@ public:
static bool checkPartialMappingIdx(PartialMappingIdx FirstAlias,
PartialMappingIdx LastAlias,
- ArrayRef<PartialMappingIdx> Order) {
- if (Order.front() != FirstAlias)
- return false;
- if (Order.back() != LastAlias)
- return false;
- if (Order.front() > Order.back())
- return false;
+ ArrayRef<PartialMappingIdx> Order);
- PartialMappingIdx Previous = Order.front();
- bool First = true;
- for (const auto &Current : Order) {
- if (First) {
- First = false;
- continue;
- }
- if (Previous + 1 != Current)
- return false;
- Previous = Current;
- }
- return true;
- }
+ static unsigned getRegBankBaseIdxOffset(unsigned RBIdx, unsigned Size);
- static unsigned getRegBankBaseIdxOffset(unsigned RBIdx, unsigned Size) {
- if (RBIdx == PMI_FirstGPR) {
- if (Size <= 32)
- return 0;
- if (Size <= 64)
- return 1;
- llvm_unreachable("Unexpected size");
- }
- if (RBIdx == PMI_FirstFPR) {
- if (Size <= 32)
- return 0;
- if (Size <= 64)
- return 1;
- if (Size <= 128)
- return 2;
- if (Size <= 256)
- return 3;
- if (Size <= 512)
- return 4;
- llvm_unreachable("Unexpected size");
- }
- llvm_unreachable("Unexpected bank");
-}
+ /// Get the pointer to the ValueMapping representing the RegisterBank
+ /// at \p RBIdx with a size of \p Size.
+ ///
+ /// The returned mapping works for instructions with the same kind of
+ /// operands for up to 3 operands.
+ ///
+ /// \pre \p RBIdx != PartialMappingIdx::None
+ static const RegisterBankInfo::ValueMapping *
+ getValueMapping(PartialMappingIdx RBIdx, unsigned Size);
+
+ /// Get the pointer to the ValueMapping of the operands of a copy
+ /// instruction from a GPR or FPR register to a GPR or FPR register
+ /// with a size of \p Size.
+ ///
+ /// If \p DstIsGPR is true, the destination of the copy is on GPR,
+ /// otherwise it is on FPR. Same thing for \p SrcIsGPR.
+ static const RegisterBankInfo::ValueMapping *
+ getCopyMapping(bool DstIsGPR, bool SrcIsGPR, unsigned Size);
};
/// This class provides the information for the target register banks.
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