[PATCH] D16829: An implementation of Swing Modulo Scheduling

[lihan via Phabricator via llvm-commits]

lihan2011 added a comment.



In https://reviews.llvm.org/D16829#639719, @bcahoon wrote:

> In https://reviews.llvm.org/D16829#638891, @lihan2011 wrote:
>
> > when i use SMS.enterRegion(MBB, MBB->begin(), MBB->getFirstTerminator(), size); it occurs 
> >  Assertion failed: VNI && "No value to read by operand"
> >  but if use SMS.enterRegion(MBB, MBB->getFirstNonPHI(), MBB->getFirstTerminator(), size2); it has no error.
> >  Am i use the wrong version of LLVM?
>
>
> You do need pass MBB->begin() to enterRegion for the pipeliner to work correctly. It looks like you're using an older version of LLVM.  I believe this issue has been fixed with a commit that was made on Dec. 4 2015 to ScheduleDAGInstrs.cpp. If you're unable to use a newer version of LLVM, I'd suggest the following the following change to addVRegUseDeps in ScheduleDAGInstrs.cpp:
>
>      // VNI will be valid because MachineOperand::readsReg() is checked by caller.
>   -  assert(VNI && "No value to read by operand");
>   -  MachineInstr *Def = LIS->getInstructionFromIndex(VNI->def);
>   +  MachineInstr *Def = (VNI ? LIS->getInstructionFromIndex(VNI->def) : 0);
>      // Phis and other noninstructions (after coalescing) have a NULL Def
>
>
> Thanks,
> Brendon


Thanks for your suggestions!

Is this problem occurs because PhiNode's use operand which is defined in ohter BasicBlocks?

AND
%vreg1<def> = PHI %vreg5, <BB#0>, %vreg4, <BB#1>; CPURegs:%vreg1,%vreg5,%vreg4
......
%vreg4<def> = ADDiu %vreg1, 4; CPURegs:%vreg4,%vreg1
When code deals with ADDiu %vreg1,it can not find the defination of %vreg1 in PHINode.
So the function void SwingSchedulerDAG::updatePhiDependences() fix this problem?

Thanks,
Lee


https://reviews.llvm.org/D16829