[llvm] r291799 - [X86] Update LLC tests for slow division bypassing (NFC)
Nikolai Bozhenov via llvm-commits
llvm-commits at lists.llvm.org
Thu Jan 12 11:29:19 PST 2017
Author: n.bozhenov
Date: Thu Jan 12 13:29:18 2017
New Revision: 291799
URL: http://llvm.org/viewvc/llvm-project?rev=291799&view=rev
Log:
[X86] Update LLC tests for slow division bypassing (NFC)
Run update_llc_test_checks.py on
CodeGen/X86/atom-bypass-slow-division.ll
CodeGen/X86/atom-bypass-slow-division-64.ll
CodeGen/X86/slow-div.ll
Differential Revision: https://reviews.llvm.org/D28469
Modified:
llvm/trunk/test/CodeGen/X86/atom-bypass-slow-division-64.ll
llvm/trunk/test/CodeGen/X86/atom-bypass-slow-division.ll
Modified: llvm/trunk/test/CodeGen/X86/atom-bypass-slow-division-64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/atom-bypass-slow-division-64.ll?rev=291799&r1=291798&r2=291799&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/atom-bypass-slow-division-64.ll (original)
+++ llvm/trunk/test/CodeGen/X86/atom-bypass-slow-division-64.ll Thu Jan 12 13:29:18 2017
@@ -1,49 +1,74 @@
-; RUN: llc < %s -mcpu=atom -march=x86-64 | FileCheck %s
-
-target triple = "x86_64-unknown-linux-gnu"
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mcpu=atom -mtriple=x86_64-unknown-linux-gnu | FileCheck %s
; Additional tests for 64-bit divide bypass
define i64 @Test_get_quotient(i64 %a, i64 %b) nounwind {
; CHECK-LABEL: Test_get_quotient:
-; CHECK: movq %rdi, %rax
-; CHECK: orq %rsi, %rax
-; CHECK-NEXT: testq $-65536, %rax
-; CHECK-NEXT: je
-; CHECK: idivq
-; CHECK: ret
-; CHECK: divw
-; CHECK: ret
+; CHECK: # BB#0:
+; CHECK-NEXT: movq %rdi, %rax
+; CHECK-NEXT: orq %rsi, %rax
+; CHECK-NEXT: testq $-65536, %rax # imm = 0xFFFF0000
+; CHECK-NEXT: je .LBB0_1
+; CHECK-NEXT: # BB#2:
+; CHECK-NEXT: movq %rdi, %rax
+; CHECK-NEXT: cqto
+; CHECK-NEXT: idivq %rsi
+; CHECK-NEXT: retq
+; CHECK-NEXT: .LBB0_1:
+; CHECK-NEXT: xorl %edx, %edx
+; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: divw %si
+; CHECK-NEXT: movzwl %ax, %eax
+; CHECK-NEXT: retq
%result = sdiv i64 %a, %b
ret i64 %result
}
define i64 @Test_get_remainder(i64 %a, i64 %b) nounwind {
; CHECK-LABEL: Test_get_remainder:
-; CHECK: movq %rdi, %rax
-; CHECK: orq %rsi, %rax
-; CHECK-NEXT: testq $-65536, %rax
-; CHECK-NEXT: je
-; CHECK: idivq
-; CHECK: ret
-; CHECK: divw
-; CHECK: ret
+; CHECK: # BB#0:
+; CHECK-NEXT: movq %rdi, %rax
+; CHECK-NEXT: orq %rsi, %rax
+; CHECK-NEXT: testq $-65536, %rax # imm = 0xFFFF0000
+; CHECK-NEXT: je .LBB1_1
+; CHECK-NEXT: # BB#2:
+; CHECK-NEXT: movq %rdi, %rax
+; CHECK-NEXT: cqto
+; CHECK-NEXT: idivq %rsi
+; CHECK-NEXT: movq %rdx, %rax
+; CHECK-NEXT: retq
+; CHECK-NEXT: .LBB1_1:
+; CHECK-NEXT: xorl %edx, %edx
+; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: divw %si
+; CHECK-NEXT: movzwl %dx, %eax
+; CHECK-NEXT: retq
%result = srem i64 %a, %b
ret i64 %result
}
define i64 @Test_get_quotient_and_remainder(i64 %a, i64 %b) nounwind {
; CHECK-LABEL: Test_get_quotient_and_remainder:
-; CHECK: movq %rdi, %rax
-; CHECK: orq %rsi, %rax
-; CHECK-NEXT: testq $-65536, %rax
-; CHECK-NEXT: je
-; CHECK: idivq
-; CHECK: divw
-; CHECK: addq
-; CHECK: ret
-; CHECK-NOT: idivq
-; CHECK-NOT: divw
+; CHECK: # BB#0:
+; CHECK-NEXT: movq %rdi, %rax
+; CHECK-NEXT: orq %rsi, %rax
+; CHECK-NEXT: testq $-65536, %rax # imm = 0xFFFF0000
+; CHECK-NEXT: je .LBB2_1
+; CHECK-NEXT: # BB#2:
+; CHECK-NEXT: movq %rdi, %rax
+; CHECK-NEXT: cqto
+; CHECK-NEXT: idivq %rsi
+; CHECK-NEXT: addq %rdx, %rax
+; CHECK-NEXT: retq
+; CHECK-NEXT: .LBB2_1:
+; CHECK-NEXT: xorl %edx, %edx
+; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: divw %si
+; CHECK-NEXT: movzwl %ax, %eax
+; CHECK-NEXT: movzwl %dx, %edx
+; CHECK-NEXT: addq %rdx, %rax
+; CHECK-NEXT: retq
%resultdiv = sdiv i64 %a, %b
%resultrem = srem i64 %a, %b
%result = add i64 %resultdiv, %resultrem
Modified: llvm/trunk/test/CodeGen/X86/atom-bypass-slow-division.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/atom-bypass-slow-division.ll?rev=291799&r1=291798&r2=291799&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/atom-bypass-slow-division.ll (original)
+++ llvm/trunk/test/CodeGen/X86/atom-bypass-slow-division.ll Thu Jan 12 13:29:18 2017
@@ -1,42 +1,75 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mcpu=atom -mtriple=i686-linux | FileCheck %s
define i32 @Test_get_quotient(i32 %a, i32 %b) nounwind {
; CHECK-LABEL: Test_get_quotient:
-; CHECK: orl %ecx, %edx
-; CHECK-NEXT: testl $-256, %edx
-; CHECK-NEXT: je
-; CHECK: idivl
-; CHECK: ret
-; CHECK: divb
-; CHECK: ret
+; CHECK: # BB#0:
+; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; CHECK-NEXT: movl %eax, %edx
+; CHECK-NEXT: orl %ecx, %edx
+; CHECK-NEXT: testl $-256, %edx
+; CHECK-NEXT: je .LBB0_1
+; CHECK-NEXT: # BB#2:
+; CHECK-NEXT: cltd
+; CHECK-NEXT: idivl %ecx
+; CHECK-NEXT: retl
+; CHECK-NEXT: .LBB0_1:
+; CHECK-NEXT: movzbl %al, %eax
+; CHECK-NEXT: # kill: %EAX<def> %EAX<kill> %AX<def>
+; CHECK-NEXT: divb %cl
+; CHECK-NEXT: movzbl %al, %eax
+; CHECK-NEXT: retl
%result = sdiv i32 %a, %b
ret i32 %result
}
define i32 @Test_get_remainder(i32 %a, i32 %b) nounwind {
; CHECK-LABEL: Test_get_remainder:
-; CHECK: orl %ecx, %edx
-; CHECK-NEXT: testl $-256, %edx
-; CHECK-NEXT: je
-; CHECK: idivl
-; CHECK: ret
-; CHECK: divb
-; CHECK: ret
+; CHECK: # BB#0:
+; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; CHECK-NEXT: movl %eax, %edx
+; CHECK-NEXT: orl %ecx, %edx
+; CHECK-NEXT: testl $-256, %edx
+; CHECK-NEXT: je .LBB1_1
+; CHECK-NEXT: # BB#2:
+; CHECK-NEXT: cltd
+; CHECK-NEXT: idivl %ecx
+; CHECK-NEXT: movl %edx, %eax
+; CHECK-NEXT: retl
+; CHECK-NEXT: .LBB1_1:
+; CHECK-NEXT: movzbl %al, %eax
+; CHECK-NEXT: # kill: %EAX<def> %EAX<kill> %AX<def>
+; CHECK-NEXT: divb %cl
+; CHECK-NEXT: movzbl %ah, %eax # NOREX
+; CHECK-NEXT: retl
%result = srem i32 %a, %b
ret i32 %result
}
define i32 @Test_get_quotient_and_remainder(i32 %a, i32 %b) nounwind {
; CHECK-LABEL: Test_get_quotient_and_remainder:
-; CHECK: orl %ecx, %edx
-; CHECK-NEXT: testl $-256, %edx
-; CHECK-NEXT: je
-; CHECK: idivl
-; CHECK: divb
-; CHECK: addl
-; CHECK: ret
-; CHECK-NOT: idivl
-; CHECK-NOT: divb
+; CHECK: # BB#0:
+; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; CHECK-NEXT: movl %eax, %edx
+; CHECK-NEXT: orl %ecx, %edx
+; CHECK-NEXT: testl $-256, %edx
+; CHECK-NEXT: je .LBB2_1
+; CHECK-NEXT: # BB#2:
+; CHECK-NEXT: cltd
+; CHECK-NEXT: idivl %ecx
+; CHECK-NEXT: addl %edx, %eax
+; CHECK-NEXT: retl
+; CHECK-NEXT: .LBB2_1:
+; CHECK-NEXT: movzbl %al, %eax
+; CHECK-NEXT: # kill: %EAX<def> %EAX<kill> %AX<def>
+; CHECK-NEXT: divb %cl
+; CHECK-NEXT: movzbl %ah, %edx # NOREX
+; CHECK-NEXT: movzbl %al, %eax
+; CHECK-NEXT: addl %edx, %eax
+; CHECK-NEXT: retl
%resultdiv = sdiv i32 %a, %b
%resultrem = srem i32 %a, %b
%result = add i32 %resultdiv, %resultrem
@@ -45,12 +78,48 @@ define i32 @Test_get_quotient_and_remain
define i32 @Test_use_div_and_idiv(i32 %a, i32 %b) nounwind {
; CHECK-LABEL: Test_use_div_and_idiv:
-; CHECK: idivl
-; CHECK: divb
-; CHECK: divl
-; CHECK: divb
-; CHECK: addl
-; CHECK: ret
+; CHECK: # BB#0:
+; CHECK-NEXT: pushl %ebx
+; CHECK-NEXT: pushl %edi
+; CHECK-NEXT: pushl %esi
+; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ebx
+; CHECK-NEXT: movl %ecx, %edi
+; CHECK-NEXT: orl %ebx, %edi
+; CHECK-NEXT: testl $-256, %edi
+; CHECK-NEXT: je .LBB3_1
+; CHECK-NEXT: # BB#2:
+; CHECK-NEXT: movl %ecx, %eax
+; CHECK-NEXT: cltd
+; CHECK-NEXT: idivl %ebx
+; CHECK-NEXT: movl %eax, %esi
+; CHECK-NEXT: testl $-256, %edi
+; CHECK-NEXT: jne .LBB3_5
+; CHECK-NEXT: jmp .LBB3_4
+; CHECK-NEXT: .LBB3_1:
+; CHECK-NEXT: movzbl %cl, %eax
+; CHECK-NEXT: # kill: %EAX<def> %EAX<kill> %AX<def>
+; CHECK-NEXT: divb %bl
+; CHECK-NEXT: movzbl %al, %esi
+; CHECK-NEXT: testl $-256, %edi
+; CHECK-NEXT: je .LBB3_4
+; CHECK-NEXT: .LBB3_5:
+; CHECK-NEXT: xorl %edx, %edx
+; CHECK-NEXT: movl %ecx, %eax
+; CHECK-NEXT: divl %ebx
+; CHECK-NEXT: jmp .LBB3_6
+; CHECK-NEXT: .LBB3_4:
+; CHECK-NEXT: movzbl %cl, %eax
+; CHECK-NEXT: # kill: %EAX<def> %EAX<kill> %AX<def>
+; CHECK-NEXT: divb %bl
+; CHECK-NEXT: movzbl %al, %eax
+; CHECK-NEXT: .LBB3_6:
+; CHECK-NEXT: addl %eax, %esi
+; CHECK-NEXT: movl %esi, %eax
+; CHECK-NEXT: popl %esi
+; CHECK-NEXT: popl %edi
+; CHECK-NEXT: popl %ebx
+; CHECK-NEXT: retl
%resultidiv = sdiv i32 %a, %b
%resultdiv = udiv i32 %a, %b
%result = add i32 %resultidiv, %resultdiv
@@ -59,34 +128,72 @@ define i32 @Test_use_div_and_idiv(i32 %a
define i32 @Test_use_div_imm_imm() nounwind {
; CHECK-LABEL: Test_use_div_imm_imm:
-; CHECK: movl $64
+; CHECK: # BB#0:
+; CHECK-NEXT: movl $64, %eax
+; CHECK-NEXT: nop
+; CHECK-NEXT: nop
+; CHECK-NEXT: nop
+; CHECK-NEXT: nop
+; CHECK-NEXT: nop
+; CHECK-NEXT: nop
+; CHECK-NEXT: retl
%resultdiv = sdiv i32 256, 4
ret i32 %resultdiv
}
define i32 @Test_use_div_reg_imm(i32 %a) nounwind {
; CHECK-LABEL: Test_use_div_reg_imm:
-; CHECK-NOT: test
-; CHECK-NOT: idiv
-; CHECK-NOT: divb
+; CHECK: # BB#0:
+; CHECK-NEXT: movl $1041204193, %eax # imm = 0x3E0F83E1
+; CHECK-NEXT: imull {{[0-9]+}}(%esp)
+; CHECK-NEXT: movl %edx, %eax
+; CHECK-NEXT: sarl $3, %edx
+; CHECK-NEXT: shrl $31, %eax
+; CHECK-NEXT: leal (%edx,%eax), %eax
+; CHECK-NEXT: retl
%resultdiv = sdiv i32 %a, 33
ret i32 %resultdiv
}
define i32 @Test_use_rem_reg_imm(i32 %a) nounwind {
; CHECK-LABEL: Test_use_rem_reg_imm:
-; CHECK-NOT: test
-; CHECK-NOT: idiv
-; CHECK-NOT: divb
+; CHECK: # BB#0:
+; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; CHECK-NEXT: movl $1041204193, %edx # imm = 0x3E0F83E1
+; CHECK-NEXT: movl %ecx, %eax
+; CHECK-NEXT: imull %edx
+; CHECK-NEXT: movl %edx, %eax
+; CHECK-NEXT: sarl $3, %edx
+; CHECK-NEXT: shrl $31, %eax
+; CHECK-NEXT: addl %eax, %edx
+; CHECK-NEXT: movl %edx, %eax
+; CHECK-NEXT: shll $5, %eax
+; CHECK-NEXT: addl %edx, %eax
+; CHECK-NEXT: subl %eax, %ecx
+; CHECK-NEXT: movl %ecx, %eax
+; CHECK-NEXT: retl
%resultrem = srem i32 %a, 33
ret i32 %resultrem
}
define i32 @Test_use_divrem_reg_imm(i32 %a) nounwind {
; CHECK-LABEL: Test_use_divrem_reg_imm:
-; CHECK-NOT: test
-; CHECK-NOT: idiv
-; CHECK-NOT: divb
+; CHECK: # BB#0:
+; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; CHECK-NEXT: movl $1041204193, %edx # imm = 0x3E0F83E1
+; CHECK-NEXT: movl %ecx, %eax
+; CHECK-NEXT: imull %edx
+; CHECK-NEXT: movl %edx, %eax
+; CHECK-NEXT: sarl $3, %edx
+; CHECK-NEXT: shrl $31, %eax
+; CHECK-NEXT: addl %eax, %edx
+; CHECK-NEXT: movl %edx, %eax
+; CHECK-NEXT: shll $5, %eax
+; CHECK-NEXT: addl %edx, %eax
+; CHECK-NEXT: subl %eax, %ecx
+; CHECK-NEXT: addl %edx, %ecx
+; CHECK-NEXT: movl %ecx, %eax
+; CHECK-NEXT: retl
%resultdiv = sdiv i32 %a, 33
%resultrem = srem i32 %a, 33
%result = add i32 %resultdiv, %resultrem
@@ -95,18 +202,44 @@ define i32 @Test_use_divrem_reg_imm(i32
define i32 @Test_use_div_imm_reg(i32 %a) nounwind {
; CHECK-LABEL: Test_use_div_imm_reg:
-; CHECK: test
-; CHECK: idiv
-; CHECK: divb
+; CHECK: # BB#0:
+; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; CHECK-NEXT: testl $-256, %ecx
+; CHECK-NEXT: je .LBB8_1
+; CHECK-NEXT: # BB#2:
+; CHECK-NEXT: movl $4, %eax
+; CHECK-NEXT: xorl %edx, %edx
+; CHECK-NEXT: idivl %ecx
+; CHECK-NEXT: retl
+; CHECK-NEXT: .LBB8_1:
+; CHECK-NEXT: movb $4, %al
+; CHECK-NEXT: movzbl %al, %eax
+; CHECK-NEXT: # kill: %EAX<def> %EAX<kill> %AX<def>
+; CHECK-NEXT: divb %cl
+; CHECK-NEXT: movzbl %al, %eax
+; CHECK-NEXT: retl
%resultdiv = sdiv i32 4, %a
ret i32 %resultdiv
}
define i32 @Test_use_rem_imm_reg(i32 %a) nounwind {
; CHECK-LABEL: Test_use_rem_imm_reg:
-; CHECK: test
-; CHECK: idiv
-; CHECK: divb
+; CHECK: # BB#0:
+; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; CHECK-NEXT: testl $-256, %ecx
+; CHECK-NEXT: je .LBB9_1
+; CHECK-NEXT: # BB#2:
+; CHECK-NEXT: movl $4, %eax
+; CHECK-NEXT: xorl %edx, %edx
+; CHECK-NEXT: idivl %ecx
+; CHECK-NEXT: retl
+; CHECK-NEXT: .LBB9_1:
+; CHECK-NEXT: movb $4, %al
+; CHECK-NEXT: movzbl %al, %eax
+; CHECK-NEXT: # kill: %EAX<def> %EAX<kill> %AX<def>
+; CHECK-NEXT: divb %cl
+; CHECK-NEXT: movzbl %al, %eax
+; CHECK-NEXT: retl
%resultdiv = sdiv i32 4, %a
ret i32 %resultdiv
}
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