[llvm] r291770 - [globalisel] Move as much RegisterBank initialization to the constructor as possible
Daniel Sanders via llvm-commits
llvm-commits at lists.llvm.org
Thu Jan 12 08:11:23 PST 2017
Author: dsanders
Date: Thu Jan 12 10:11:23 2017
New Revision: 291770
URL: http://llvm.org/viewvc/llvm-project?rev=291770&view=rev
Log:
[globalisel] Move as much RegisterBank initialization to the constructor as possible
Summary:
The register bank is now entirely initialized in the constructor. However,
we still have the hardcoded number of register classes which will be
dealt with in the TableGen patch (D27338) since we do not have access
to this information to resolve this at this stage. The number of register
classes is known to the TRI and to TableGen but the RegisterBank
constructor is too early for the former and too late for the latter.
This will be fixed when the data is tablegen-erated.
Reviewers: t.p.northover, ab, rovka, qcolombet
Subscribers: aditya_nandakumar, kristof.beyls, vkalintiris, llvm-commits, dberris
Differential Revision: https://reviews.llvm.org/D27809
Modified:
llvm/trunk/include/llvm/CodeGen/GlobalISel/RegisterBank.h
llvm/trunk/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h
llvm/trunk/lib/CodeGen/GlobalISel/RegisterBank.cpp
llvm/trunk/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
llvm/trunk/lib/Target/AArch64/AArch64GenRegisterBankInfo.def
llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp
Modified: llvm/trunk/include/llvm/CodeGen/GlobalISel/RegisterBank.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/GlobalISel/RegisterBank.h?rev=291770&r1=291769&r2=291770&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/GlobalISel/RegisterBank.h (original)
+++ llvm/trunk/include/llvm/CodeGen/GlobalISel/RegisterBank.h Thu Jan 12 10:11:23 2017
@@ -41,11 +41,8 @@ private:
friend RegisterBankInfo;
public:
- /// The default constructor will leave the object in
- /// an invalid state. I.e. isValid() == false.
- /// The fields must be updated to fix that and only
- /// RegisterBankInfo instances are allowed to do that
- RegisterBank();
+ RegisterBank(unsigned ID, const char *Name, unsigned Size,
+ const uint32_t *ContainedRegClasses);
/// Get the identifier of this register bank.
unsigned getID() const { return ID; }
Modified: llvm/trunk/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h?rev=291770&r1=291769&r2=291770&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h (original)
+++ llvm/trunk/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h Thu Jan 12 10:11:23 2017
@@ -396,9 +396,6 @@ protected:
llvm_unreachable("This constructor should not be executed");
}
- void setRegBankData(unsigned ID, const char *Name, unsigned Size,
- const uint32_t *CoveredClasses);
-
/// Get the register bank identified by \p ID.
RegisterBank &getRegBank(unsigned ID) {
assert(ID < getNumRegBanks() && "Accessing an unknown register bank");
Modified: llvm/trunk/lib/CodeGen/GlobalISel/RegisterBank.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/RegisterBank.cpp?rev=291770&r1=291769&r2=291770&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/GlobalISel/RegisterBank.cpp (original)
+++ llvm/trunk/lib/CodeGen/GlobalISel/RegisterBank.cpp Thu Jan 12 10:11:23 2017
@@ -19,7 +19,12 @@ using namespace llvm;
const unsigned RegisterBank::InvalidID = UINT_MAX;
-RegisterBank::RegisterBank() : ID(InvalidID), Name(nullptr), Size(0) {}
+RegisterBank::RegisterBank(unsigned ID, const char *Name, unsigned Size,
+ const uint32_t *CoveredClasses)
+ : ID(ID), Name(Name), Size(Size) {
+ ContainedRegClasses.resize(200);
+ ContainedRegClasses.setBitsInMask(CoveredClasses);
+}
bool RegisterBank::verify(const TargetRegisterInfo &TRI) const {
assert(isValid() && "Invalid register bank");
Modified: llvm/trunk/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp?rev=291770&r1=291769&r2=291770&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp (original)
+++ llvm/trunk/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp Thu Jan 12 10:11:23 2017
@@ -56,8 +56,10 @@ RegisterBankInfo::RegisterBankInfo(Regis
unsigned NumRegBanks)
: RegBanks(RegBanks), NumRegBanks(NumRegBanks) {
#ifndef NDEBUG
- for (unsigned Idx = 0, End = getNumRegBanks(); Idx != End; ++Idx)
+ for (unsigned Idx = 0, End = getNumRegBanks(); Idx != End; ++Idx) {
assert(RegBanks[Idx] != nullptr && "Invalid RegisterBank");
+ assert(RegBanks[Idx]->isValid() && "RegisterBank should be valid");
+ }
#endif // NDEBUG
}
@@ -81,17 +83,6 @@ bool RegisterBankInfo::verify(const Targ
return true;
}
-void RegisterBankInfo::setRegBankData(unsigned ID, const char *Name,
- unsigned Size,
- const uint32_t *CoveredClasses) {
- RegisterBank &RB = getRegBank(ID);
- RB.ID = ID;
- RB.Name = Name;
- RB.Size = Size;
- RB.ContainedRegClasses.resize(200);
- RB.ContainedRegClasses.setBitsInMask(CoveredClasses);
-}
-
const RegisterBank *
RegisterBankInfo::getRegBank(unsigned Reg, const MachineRegisterInfo &MRI,
const TargetRegisterInfo &TRI) const {
Modified: llvm/trunk/lib/Target/AArch64/AArch64GenRegisterBankInfo.def
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64GenRegisterBankInfo.def?rev=291770&r1=291769&r2=291770&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64GenRegisterBankInfo.def (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64GenRegisterBankInfo.def Thu Jan 12 10:11:23 2017
@@ -141,9 +141,9 @@ const uint32_t CCRCoverageData[] = {
0,
};
-RegisterBank GPRRegBank;
-RegisterBank FPRRegBank;
-RegisterBank CCRRegBank;
+RegisterBank GPRRegBank(AArch64::GPRRegBankID, "GPR", 64, GPRCoverageData);
+RegisterBank FPRRegBank(AArch64::FPRRegBankID, "FPR", 512, FPRCoverageData);
+RegisterBank CCRRegBank(AArch64::CCRRegBankID, "CCR", 32, CCRCoverageData);
RegisterBank *RegBanks[] = {&GPRRegBank, &FPRRegBank, &CCRRegBank};
Modified: llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp?rev=291770&r1=291769&r2=291770&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp Thu Jan 12 10:11:23 2017
@@ -41,25 +41,30 @@ AArch64RegisterBankInfo::AArch64Register
if (AlreadyInit)
return;
AlreadyInit = true;
- // The GPR register bank is fully defined by all the registers in
- // GR64all + its subclasses.
- setRegBankData(AArch64::GPRRegBankID, "GPR", 64, AArch64::GPRCoverageData);
+
const RegisterBank &RBGPR = getRegBank(AArch64::GPRRegBankID);
(void)RBGPR;
assert(&AArch64::GPRRegBank == &RBGPR &&
"The order in RegBanks is messed up");
+
+ const RegisterBank &RBFPR = getRegBank(AArch64::FPRRegBankID);
+ (void)RBFPR;
+ assert(&AArch64::FPRRegBank == &RBFPR &&
+ "The order in RegBanks is messed up");
+
+ const RegisterBank &RBCCR = getRegBank(AArch64::CCRRegBankID);
+ (void)RBCCR;
+ assert(&AArch64::CCRRegBank == &RBCCR &&
+ "The order in RegBanks is messed up");
+
+ // The GPR register bank is fully defined by all the registers in
+ // GR64all + its subclasses.
assert(RBGPR.covers(*TRI.getRegClass(AArch64::GPR32RegClassID)) &&
"Subclass not added?");
assert(RBGPR.getSize() == 64 && "GPRs should hold up to 64-bit");
// The FPR register bank is fully defined by all the registers in
// GR64all + its subclasses.
- setRegBankData(AArch64::FPRRegBankID, "FPR", 512, AArch64::FPRCoverageData);
-
- const RegisterBank &RBFPR = getRegBank(AArch64::FPRRegBankID);
- (void)RBFPR;
- assert(&AArch64::FPRRegBank == &RBFPR &&
- "The order in RegBanks is messed up");
assert(RBFPR.covers(*TRI.getRegClass(AArch64::QQRegClassID)) &&
"Subclass not added?");
assert(RBFPR.covers(*TRI.getRegClass(AArch64::FPR64RegClassID)) &&
@@ -67,12 +72,6 @@ AArch64RegisterBankInfo::AArch64Register
assert(RBFPR.getSize() == 512 &&
"FPRs should hold up to 512-bit via QQQQ sequence");
- // Initialize the CCR bank.
- setRegBankData(AArch64::CCRRegBankID, "CCR", 32, AArch64::CCRCoverageData);
- const RegisterBank &RBCCR = getRegBank(AArch64::CCRRegBankID);
- (void)RBCCR;
- assert(&AArch64::CCRRegBank == &RBCCR &&
- "The order in RegBanks is messed up");
assert(RBCCR.covers(*TRI.getRegClass(AArch64::CCRRegClassID)) &&
"Class not added?");
assert(RBCCR.getSize() == 32 && "CCR should hold up to 32-bit");
Modified: llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp?rev=291770&r1=291769&r2=291770&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp Thu Jan 12 10:11:23 2017
@@ -55,7 +55,7 @@ const uint32_t GPRCoverageData[] = {
0,
};
-RegisterBank GPRRegBank;
+RegisterBank GPRRegBank(ARM::GPRRegBankID, "GPRB", 32, ARM::GPRCoverageData);
RegisterBank *RegBanks[] = {&GPRRegBank};
RegisterBankInfo::PartialMapping GPRPartialMapping{0, 32, GPRRegBank};
@@ -77,11 +77,11 @@ ARMRegisterBankInfo::ARMRegisterBankInfo
return;
AlreadyInit = true;
- // Initialize the GPR bank.
- setRegBankData(ARM::GPRRegBankID, "GPRB", 32, ARM::GPRCoverageData);
const RegisterBank &RBGPR = getRegBank(ARM::GPRRegBankID);
(void)RBGPR;
assert(&ARM::GPRRegBank == &RBGPR && "The order in RegBanks is messed up");
+
+ // Initialize the GPR bank.
assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRRegClassID)) &&
"Subclass not added?");
assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRwithAPSRRegClassID)) &&
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