[PATCH] D28152: Cortex-A57 scheduling model for ARM backend (AArch32)

[Andrew Zhogin via Phabricator via llvm-commits]

andrew.zhogin added a comment.

In https://reviews.llvm.org/D28152#642900, @rovka wrote:

> Hi,
>
> This looks like a lot of work :) Could you please split it up into smaller patches, e.g. to separate the mechanical scheduling definitions from the more structural changes?
>
> Thanks,
> Diana


I'm not quite understand what is "more structural changes". New functions in ARMBaseInstrInfo? They are required for scheduling predicates to handle situations like: "Load, register offset, plus", "Load, register offset, minus", "Load, scaled register offset, plus LSL2", ...
And they are not used by any side code.

For example:

  // For "Load, register offset, minus" we need +1cyc, +1I
  def A57WriteLdrAm3 : SchedWriteVariant<[
    SchedVar<IsLdrAm3NegRegOffPred, [A57Write_5cyc_1I_1L]>,
    SchedVar<NoSchedPred,           [A57Write_4cyc_1L]>
  ]>;
  def : InstRW<[A57WriteLdrAm3], (instregex "LDR(H|SH|SB)$")>;


https://reviews.llvm.org/D28152