[PATCH] D28152: Cortex-A57 scheduling model for ARM backend (AArch32)

[Andrew Zhogin via Phabricator via llvm-commits]

andrew.zhogin added inline comments.


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Comment at: lib/Target/ARM/ARMScheduleA57.td:86
+  // Enable partial & runtime unrolling. The magic number is chosen based on
+  // experiments and benchmarking data.
+  let LoopMicroOpBufferSize = 16;
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rovka wrote:
> Cool, can you share this data?
"Common description and scheduling model parameters taken from AArch64" (for the same processor, AArch64SchedA57.td). I will delete this comment.


https://reviews.llvm.org/D28152