[PATCH] D28198: [X86] Replace AND+IMM64 with SRL/SHL

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added a comment.

A few final minors



================
Comment at: lib/Target/X86/X86ISelLowering.cpp:15892
+
+        if (Mask.countLeadingOnes() + Mask.countTrailingZeros() ==
+            Mask.getBitWidth()) {
----------------
Pull out Mask.countTrailingZeros()  to avoid duplication?


================
Comment at: lib/Target/X86/X86ISelLowering.cpp:15896
+                 "Shift amount should be less than the type width");
+          SDValue ShAmt = DAG.getConstant(Mask.countTrailingZeros(), dl, VT);
+          Op = DAG.getNode(ISD::SRL, dl, VT, Op0, ShAmt);
----------------
Use getScalarShiftAmountTy for the type


================
Comment at: lib/Target/X86/X86ISelLowering.cpp:15901
+
+        if (Mask.countLeadingZeros() + Mask.countTrailingOnes() ==
+            Mask.getBitWidth()) {
----------------
Pull out Mask.countLeadingZeros() to avoid duplication?


================
Comment at: lib/Target/X86/X86ISelLowering.cpp:15905
+                 "Shift amount should be less than the type width");
+          SDValue ShAmt = DAG.getConstant(Mask.countLeadingZeros(), dl, VT);
+          Op = DAG.getNode(ISD::SHL, dl, VT, Op0, ShAmt);
----------------
Use getScalarShiftAmountTy for the type


https://reviews.llvm.org/D28198