[PATCH] D22398: MIRParser: Allow register class specification on operand

[Quentin Colombet via llvm-commits]

Agreed.
> On Jan 10, 2017, at 5:30 PM, Matthias Braun via Phabricator <reviews at reviews.llvm.org> wrote:
> 
> MatzeB added a comment.
> 
> Thanks for the review.
> 
> 
> 
> ================
> Comment at: test/CodeGen/MIR/X86/register-operand-class.mir:19
> +    %rdx = COPY %1
> +    %2 = COPY %ecx
> +    %ecx = COPY %2 : gr32
> ----------------
> qcolombet wrote:
>> Just a thought, shouldn't we make the class/bank on the definition mandatory?
> Yeah, enforcing this for every def (and function live-in declaration) would be a good thing. First however we need a patch that lets the MIRPrinter use the new syntax here.
> 
> 
> Repository:
>  rL LLVM
> 
> https://reviews.llvm.org/D22398
> 
> 
>