[PATCH] D22398: MIRParser: Allow register class specification on operand

[Quentin Colombet via Phabricator via llvm-commits]

qcolombet accepted this revision.
qcolombet added a comment.
This revision is now accepted and ready to land.

LGTM



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Comment at: test/CodeGen/MIR/X86/register-operand-class.mir:19
+    %rdx = COPY %1
+    %2 = COPY %ecx
+    %ecx = COPY %2 : gr32
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Just a thought, shouldn't we make the class/bank on the definition mandatory?


Repository:
  rL LLVM

https://reviews.llvm.org/D22398