[PATCH] D28527: Check for register clobbers when merging a vreg live range with a reserved physreg in RegisterCoalescer.

[James Y Knight via Phabricator via llvm-commits]

jyknight created this revision.
jyknight added a reviewer: qcolombet.
jyknight added a subscriber: llvm-commits.
Herald added a subscriber: MatzeB.

Previously, we only checked for clobbers when merging into a READ of
the physreg, but not when merging from a WRITE to the physreg.


https://reviews.llvm.org/D28527

Files:
  lib/CodeGen/RegisterCoalescer.cpp
  test/CodeGen/SPARC/register-clobber.ll


Index: test/CodeGen/SPARC/register-clobber.ll
===================================================================
--- /dev/null
+++ test/CodeGen/SPARC/register-clobber.ll
@@ -0,0 +1,35 @@
+; RUN: llc -march=sparc < %s | FileCheck %s
+
+;; Verify that g1 (the output of first asm) is properly understood to
+;; be clobbered by the call instruction, and moved out of the way
+;; before it. (NOTE: remember delay slot; mov executes before call)
+
+; CHECK-LABEL: test1:
+; CHECK: ta       9
+; CHECK: call dosomething
+; CHECK: mov      %g1, %i0
+
+define i32 @test1() nounwind {
+entry:
+  %0 = tail call i32 asm sideeffect "ta $1", "={r1},i"(i32 9) nounwind
+  tail call void @dosomething() nounwind
+  ret i32 %0
+}
+
+;; Also check using the value.
+; CHECK-LABEL: test2:
+; CHECK: ta       9
+; CHECK: call dosomething
+; CHECK: mov      %g1, %i0
+; CHECK: mov      %i0, %g1
+; CHECK: ta       10
+
+define void @test2() local_unnamed_addr nounwind {
+entry:
+  %0 = tail call i32 asm sideeffect "ta $1", "={r1},i"(i32 9) nounwind
+  tail call void @dosomething() nounwind
+  tail call void asm sideeffect "ta $0", "i,{r1}"(i32 10, i32 %0) nounwind
+  ret void
+}
+
+declare void @dosomething() local_unnamed_addr nounwind
Index: lib/CodeGen/RegisterCoalescer.cpp
===================================================================
--- lib/CodeGen/RegisterCoalescer.cpp
+++ lib/CodeGen/RegisterCoalescer.cpp
@@ -1582,6 +1582,14 @@
         return false;
       }
     }
+
+    // We must also check for overlaps with regmask clobbers.
+    BitVector RegMaskUsable;
+    if (LIS->checkRegMaskInterference(RHS, RegMaskUsable) &&
+        !RegMaskUsable.test(DstReg)) {
+      DEBUG(dbgs() << "\t\tRegMask interference\n");
+      return false;
+    }
   }
 
   // Skip any value computations, we are not adding new values to the
@@ -1616,14 +1624,6 @@
           DEBUG(dbgs() << "\t\tInterference (read): " << *MI);
           return false;
         }
-
-        // We must also check for clobbers caused by regmasks.
-        for (const auto &MO : MI->operands()) {
-          if (MO.isRegMask() && MO.clobbersPhysReg(DstReg)) {
-            DEBUG(dbgs() << "\t\tInterference (regmask clobber): " << *MI);
-            return false;
-          }
-        }
       }
     }
 


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