[llvm] r291566 - [mips] Honour -mno-odd-spreg for vector splat (again)
Simon Dardis via llvm-commits
llvm-commits at lists.llvm.org
Tue Jan 10 07:53:10 PST 2017
Author: sdardis
Date: Tue Jan 10 09:53:10 2017
New Revision: 291566
URL: http://llvm.org/viewvc/llvm-project?rev=291566&view=rev
Log:
[mips] Honour -mno-odd-spreg for vector splat (again)
Previous the lowering of FILL_FW would use the MSA128W register class when
performing a vector splat. Instead it should be honouring -mno-odd-spreg and
only use the even registers when performing a splat from word to vector
register.
Logical follow-on from r230235.
This fixes PR/31369.
A previous commit was missing the test case and had another differential
in it.
Reviewers: slthakur
Differential Revision: https://reviews.llvm.org/D28373
Added:
llvm/trunk/test/CodeGen/Mips/msa/msa-nooddspreg.ll
Modified:
llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp
Modified: llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp?rev=291566&r1=291565&r2=291566&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp Tue Jan 10 09:53:10 2017
@@ -3377,8 +3377,12 @@ MipsSETargetLowering::emitFILL_FW(Machin
DebugLoc DL = MI.getDebugLoc();
unsigned Wd = MI.getOperand(0).getReg();
unsigned Fs = MI.getOperand(1).getReg();
- unsigned Wt1 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
- unsigned Wt2 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
+ unsigned Wt1 = RegInfo.createVirtualRegister(
+ Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass
+ : &Mips::MSA128WEvensRegClass);
+ unsigned Wt2 = RegInfo.createVirtualRegister(
+ Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass
+ : &Mips::MSA128WEvensRegClass);
BuildMI(*BB, MI, DL, TII->get(Mips::IMPLICIT_DEF), Wt1);
BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_SUBREG), Wt2)
Added: llvm/trunk/test/CodeGen/Mips/msa/msa-nooddspreg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/msa-nooddspreg.ll?rev=291566&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/msa-nooddspreg.ll (added)
+++ llvm/trunk/test/CodeGen/Mips/msa/msa-nooddspreg.ll Tue Jan 10 09:53:10 2017
@@ -0,0 +1,55 @@
+; RUN: llc -march=mips -mcpu=mips32r5 -mattr=+fp64,+msa,+nooddspreg < %s | FileCheck %s
+
+; Test that the register allocator honours +nooddspreg and does not pick an odd
+; single precision subregister of an MSA register.
+
+ at f1 = external global float
+
+ at f2 = external global float
+
+ at v3 = external global <4 x float>
+
+ at d1 = external global double
+
+define void @test() {
+; CHECK-LABEL: test:
+entry:
+; CHECK-NOT: lwc1 $f{{[13579]+}}
+; CHECK: lwc1 $f{{[02468]+}}
+ %0 = load float, float * @f1
+ %1 = insertelement <4 x float> undef, float %0, i32 0
+ %2 = insertelement <4 x float> %1, float %0, i32 1
+ %3 = insertelement <4 x float> %2, float %0, i32 2
+ %4 = insertelement <4 x float> %3, float %0, i32 3
+
+; CHECK-NOT: lwc1 $f{{[13579]+}}
+; CHECK: lwc1 $f{{[02468]+}}
+ %5 = load float, float * @f2
+ %6 = insertelement <4 x float> undef, float %5, i32 0
+ %7 = insertelement <4 x float> %6, float %5, i32 1
+ %8 = insertelement <4 x float> %7, float %5, i32 2
+ %9 = insertelement <4 x float> %8, float %5, i32 3
+
+ %10 = fadd <4 x float> %4, %9
+ store <4 x float> %10, <4 x float> * @v3
+ ret void
+}
+
+; Test that the register allocator hnours +noodspreg and does not pick an odd
+; single precision register for a load to perform a conversion to a double.
+
+define void @test2() {
+; CHECK-LABEL: test2:
+entry:
+; CHECK-NOT: lwc1 $f{{[13579]+}}
+; CHECK: lwc1 $f{{[02468]+}}
+ %0 = load float, float * @f1
+ %1 = fpext float %0 to double
+; CHECK-NOT: lwc1 $f{{[13579]+}}
+; CHECK: lwc1 $f{{[02468]+}}
+ %2 = load float, float * @f2
+ %3 = fpext float %2 to double
+ %4 = fadd double %1, %3
+ store double%4, double * @d1
+ ret void
+}
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