[PATCH] D27998: [AArch64] Consider all vector types for FeatureSlowMisaligned128Store

[Ahmed Bougacha via Phabricator via llvm-commits]

ab added a reviewer: mzolotukhin.
ab added a comment.

Digging around, here's my summary of the various comments:

- with FeatureSlowMisaligned128Store, 128-bit misaligned stores are split because they're slow
- v2i64 is special because it's generated by memcpy lowering; splitting was disabled for that type because it turned out to cause regressions
- to minimize the amount of other (non-memcpy) misaligned v2i64 stores, the cost model was taught to penalize them heavily; otherwise, these aren't split and cause slowdowns.

>From that perspective, penalizing other 128-bit types sounds reasonable to me, but I don't have any concrete cyclone numbers.


Repository:
  rL LLVM

https://reviews.llvm.org/D27998