[PATCH] D28135: SelectionDAG: Fix in legalization of UMAX/SMAX/UMIN/SMIN. Solves PR31486.
Bjorn Pettersson via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Jan 9 04:14:52 PST 2017
This revision was automatically updated to reflect the committed changes.
Closed by commit rL291441: [SelectionDAG] Fix in legalization of UMAX/SMAX/UMIN/SMIN. Solves PR31486. (authored by bjope).
Changed prior to commit:
https://reviews.llvm.org/D28135?vs=83196&id=83610#toc
Repository:
rL LLVM
https://reviews.llvm.org/D28135
Files:
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
llvm/trunk/test/CodeGen/AMDGPU/r600-legalize-umax-bug.ll
Index: llvm/trunk/test/CodeGen/AMDGPU/r600-legalize-umax-bug.ll
===================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/r600-legalize-umax-bug.ll
+++ llvm/trunk/test/CodeGen/AMDGPU/r600-legalize-umax-bug.ll
@@ -0,0 +1,16 @@
+; RUN: llc -march=r600 -mcpu=cypress -start-after safe-stack %s -o - | FileCheck %s
+; Don't crash
+
+; CHECK: MAX_UINT
+define void @test(i64 addrspace(1)* %out) {
+bb:
+ store i64 2, i64 addrspace(1)* %out
+ %tmp = load i64, i64 addrspace(1)* %out
+ br label %jump
+
+jump: ; preds = %bb
+ %tmp1 = icmp ugt i64 %tmp, 4
+ %umax = select i1 %tmp1, i64 %tmp, i64 4
+ store i64 %umax, i64 addrspace(1)* %out
+ ret void
+}
Index: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
===================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -1714,7 +1714,7 @@
EVT CCT = getSetCCResultType(NVT);
// Hi part is always the same op
- Hi = DAG.getNode(N->getOpcode(), DL, {NVT, NVT}, {LHSH, RHSH});
+ Hi = DAG.getNode(N->getOpcode(), DL, NVT, {LHSH, RHSH});
// We need to know whether to select Lo part that corresponds to 'winning'
// Hi part or if Hi parts are equal.
@@ -1725,7 +1725,7 @@
SDValue LoCmp = DAG.getSelect(DL, NVT, IsHiLeft, LHSL, RHSL);
// Recursed Lo part if Hi parts are equal, this uses unsigned version
- SDValue LoMinMax = DAG.getNode(LoOpc, DL, {NVT, NVT}, {LHSL, RHSL});
+ SDValue LoMinMax = DAG.getNode(LoOpc, DL, NVT, {LHSL, RHSL});
Lo = DAG.getSelect(DL, NVT, IsHiEq, LoMinMax, LoCmp);
}
-------------- next part --------------
A non-text attachment was scrubbed...
Name: D28135.83610.patch
Type: text/x-patch
Size: 1715 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20170109/415a1cd2/attachment.bin>
More information about the llvm-commits
mailing list