[PATCH] D28194: [ARM] Classification Improvements to ARM Sched-Models. NFCI.

[Javed Absar via Phabricator via llvm-commits]

javed.absar updated this revision to Diff 83595.
javed.absar added a comment.

Hi Renato:
Thanks. I have removed the commented lines and unnecessary white-space, as you recommended.
Best Regards
Javed


https://reviews.llvm.org/D28194

Files:
  lib/Target/ARM/ARMScheduleSwift.td


Index: lib/Target/ARM/ARMScheduleSwift.td
===================================================================
--- lib/Target/ARM/ARMScheduleSwift.td
+++ lib/Target/ARM/ARMScheduleSwift.td
@@ -304,7 +304,6 @@
   def : InstRW <[SwiftDiv],
         (instregex "SDIV", "UDIV", "t2SDIV", "t2UDIV")>;
 
-
   // 4.2.19 Integer Load Single Element
   // 4.2.20 Integer Load Signextended
   def SwiftWriteP2P01ThreeCycle : SchedWriteRes<[SwiftUnitP2, SwiftUnitP01]> {
@@ -606,8 +605,6 @@
 
   // 4.2.36 Advanced SIMD and VFP, Convert
   def : InstRW<[SwiftWriteP1FourCycle], (instregex "VCVT", "V(S|U)IT", "VTO(S|U)")>;
-  // Fixpoint conversions.
-  //def : WriteRes<WriteCvtFP, [SwiftUnitP1]> { let Latency = 4; }
 
   // 4.2.37 Advanced SIMD and VFP, Move
   def : InstRW<[SwiftWriteP0TwoCycle],


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