[PATCH] D28017: AMD family 17h (znver1) enablement

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added a comment.

A few minors but I don't have any major concerns.

Add znver1 tests to llvm\test\CodeGen\X86\slow-unaligned-mem.ll



================
Comment at: lib/Target/X86/X86.td:764
+// Zen
+def: ProcessorModel<"znver1", BtVer2Model, [
+  FeatureADX,
----------------
Are we happy with alphabetical ordering of the feature bits? We don't seem to be consistent for this for many targets at all.


================
Comment at: lib/Target/X86/X86.td:767
+  FeatureAES,
+  FeatureAVX,
+  FeatureAVX2,
----------------
Remove FeatureAVX - it will be implicitly included as FeatureAVX2 is set.


================
Comment at: lib/Target/X86/X86.td:777
+  FeatureFXSR,
+  FeatureFastLZCNT,
+  FeatureLAHFSAHF,
----------------
Add znver1 to llvm\test\CodeGen\X86\lzcnt-zext-cmp.ll 


================
Comment at: lib/Target/X86/X86.td:791
+  FeatureSSE4A,
+  FeatureSSSE3,
+  FeatureSlowSHLD,
----------------
Remove FeatureSSSE3 - it will be implicitly included as FeatureAVX2 is set.


================
Comment at: lib/Target/X86/X86.td:792
+  FeatureSSSE3,
+  FeatureSlowSHLD,
+  FeatureX87,
----------------
Add znver1 to llvm\test\CodeGen\X86\x86-64-double-shifts-var.ll as you're testing for slow SHLD


https://reviews.llvm.org/D28017