[llvm] r291244 - [X86][SSE] Simplify float domain requirement in unary shuffle matching.

Simon Pilgrim via llvm-commits llvm-commits at lists.llvm.org
Fri Jan 6 09:01:00 PST 2017


Author: rksimon
Date: Fri Jan  6 11:00:59 2017
New Revision: 291244

URL: http://llvm.org/viewvc/llvm-project?rev=291244&view=rev
Log:
[X86][SSE] Simplify float domain requirement in unary shuffle matching.

The AVX1-only limit is never actually required in matchUnaryVectorShuffle

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=291244&r1=291243&r2=291244&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Jan  6 11:00:59 2017
@@ -25961,8 +25961,7 @@ static bool matchUnaryVectorShuffle(MVT
                                     unsigned &Shuffle, MVT &SrcVT, MVT &DstVT) {
   unsigned NumMaskElts = Mask.size();
   unsigned MaskEltSize = MaskVT.getScalarSizeInBits();
-  bool FloatDomain = MaskVT.isFloatingPoint() ||
-                     (!Subtarget.hasAVX2() && MaskVT.is256BitVector());
+  bool FloatDomain = MaskVT.isFloatingPoint();
 
   // Match against a VZEXT_MOVL instruction, SSE1 only supports 32-bits (MOVSS).
   if (((MaskEltSize == 32) || (MaskEltSize == 64 && Subtarget.hasSSE2())) &&




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