[llvm] r291196 - [SelectionDAG] Correctly transform range metadata to AssertZExt

[David Majnemer via llvm-commits]

Author: majnemer
Date: Thu Jan  5 18:11:46 2017
New Revision: 291196

URL: http://llvm.org/viewvc/llvm-project?rev=291196&view=rev
Log:
[SelectionDAG] Correctly transform range metadata to AssertZExt

We used the logBase2 of the high instead of the ceilLogBase2 resulting
in the wrong result for certain values.  For example, it resulted in an
i1 AssertZExt when the exclusive portion of the range was 3.

Added:
    llvm/trunk/test/CodeGen/NVPTX/tid-range.ll
Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=291196&r1=291195&r2=291196&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Thu Jan  5 18:11:46 2017
@@ -7344,7 +7344,7 @@ SDValue SelectionDAGBuilder::lowerRangeT
     return Op;
 
   Constant *Hi = cast<ConstantAsMetadata>(Range->getOperand(1))->getValue();
-  unsigned Bits = cast<ConstantInt>(Hi)->getValue().logBase2();
+  unsigned Bits = cast<ConstantInt>(Hi)->getValue().ceilLogBase2();
 
   EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), Bits);
 

Added: llvm/trunk/test/CodeGen/NVPTX/tid-range.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/NVPTX/tid-range.ll?rev=291196&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/NVPTX/tid-range.ll (added)
+++ llvm/trunk/test/CodeGen/NVPTX/tid-range.ll Thu Jan  5 18:11:46 2017
@@ -0,0 +1,18 @@
+; RUN: llc < %s -march=nvptx64 | FileCheck %s
+declare i32 @get_register()
+
+define i1 @test1() {
+entry:
+  %call = call i32 @llvm.nvvm.read.ptx.sreg.tid.x(), !range !0
+  %cmp = icmp eq i32 %call, 1
+  ret i1 %cmp
+}
+
+; CHECK-LABEL: test1(
+; CHECK: setp.eq.s32  %p1, %r1, 1;
+; CHECK: selp.u32     %[[R:.+]], 1, 0, %p1;
+; CHECK: st.param.b32 [func_retval0+0], %[[R]];
+
+declare i32 @llvm.nvvm.read.ptx.sreg.tid.x()
+
+!0 = !{ i32 0, i32 3 }