[llvm] r291168 - Revert "Reapply r291025 ("AMDGPU: Remove unneccessary intermediate vector")"
Evgeniy Stepanov via llvm-commits
llvm-commits at lists.llvm.org
Thu Jan 5 11:51:13 PST 2017
Author: eugenis
Date: Thu Jan 5 13:51:13 2017
New Revision: 291168
URL: http://llvm.org/viewvc/llvm-project?rev=291168&view=rev
Log:
Revert "Reapply r291025 ("AMDGPU: Remove unneccessary intermediate vector")"
Summary: This reverts commit r291144. It breaks build bots.
http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-autoconf/builds/3270, http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-fuzzer/builds/2058
lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp:1638:12: error: could not convert ‘(const unsigned int*)(& Variants)’ from ‘const unsigned int*’ to ‘llvm::ArrayRef<unsigned int>’
return Variants;
Reviewers: eugenis, tstellarAMD
Patch by Alex Shlyapnikov.
Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, tony-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D28372
Modified:
llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
Modified: llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp?rev=291168&r1=291167&r2=291168&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp Thu Jan 5 13:51:13 2017
@@ -822,7 +822,6 @@ public:
bool isForcedVOP3() const { return ForcedEncodingSize == 64; }
bool isForcedDPP() const { return ForcedDPP; }
bool isForcedSDWA() const { return ForcedSDWA; }
- ArrayRef<unsigned> getMatchedVariants() const;
std::unique_ptr<AMDGPUOperand> parseRegister();
bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
@@ -1631,44 +1630,31 @@ unsigned AMDGPUAsmParser::checkTargetMat
return Match_Success;
}
-// What asm variants we should check
-ArrayRef<unsigned> AMDGPUAsmParser::getMatchedVariants() const {
- if (getForcedEncodingSize() == 32) {
- static const unsigned Variants[] = {AMDGPUAsmVariants::DEFAULT};
- return Variants;
- }
-
- if (isForcedVOP3()) {
- static const unsigned Variants[] = {AMDGPUAsmVariants::VOP3};
- return Variants;
- }
-
- if (isForcedSDWA()) {
- static const unsigned Variants[] = {AMDGPUAsmVariants::SDWA};
- return Variants;
- }
-
- if (isForcedDPP()) {
- static const unsigned Variants[] = {AMDGPUAsmVariants::DPP};
- return Variants;
- }
-
- static const unsigned Variants[] = {
- AMDGPUAsmVariants::DEFAULT, AMDGPUAsmVariants::VOP3,
- AMDGPUAsmVariants::SDWA, AMDGPUAsmVariants::DPP
- };
-
- return Variants;
-}
-
bool AMDGPUAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
OperandVector &Operands,
MCStreamer &Out,
uint64_t &ErrorInfo,
bool MatchingInlineAsm) {
+ // What asm variants we should check
+ std::vector<unsigned> MatchedVariants;
+ if (getForcedEncodingSize() == 32) {
+ MatchedVariants = {AMDGPUAsmVariants::DEFAULT};
+ } else if (isForcedVOP3()) {
+ MatchedVariants = {AMDGPUAsmVariants::VOP3};
+ } else if (isForcedSDWA()) {
+ MatchedVariants = {AMDGPUAsmVariants::SDWA};
+ } else if (isForcedDPP()) {
+ MatchedVariants = {AMDGPUAsmVariants::DPP};
+ } else {
+ MatchedVariants = {AMDGPUAsmVariants::DEFAULT,
+ AMDGPUAsmVariants::VOP3,
+ AMDGPUAsmVariants::SDWA,
+ AMDGPUAsmVariants::DPP};
+ }
+
MCInst Inst;
unsigned Result = Match_Success;
- for (auto Variant : getMatchedVariants()) {
+ for (auto Variant : MatchedVariants) {
uint64_t EI;
auto R = MatchInstructionImpl(Operands, Inst, EI, MatchingInlineAsm,
Variant);
@@ -3500,7 +3486,7 @@ void AMDGPUAsmParser::cvtSDWA(MCInst &In
for (unsigned E = Operands.size(); I != E; ++I) {
AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);
// Add the register arguments
- if ((BasicInstType == SIInstrFlags::VOPC ||
+ if ((BasicInstType == SIInstrFlags::VOPC ||
BasicInstType == SIInstrFlags::VOP2)&&
Op.isReg() &&
Op.Reg.RegNo == AMDGPU::VCC) {
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