[PATCH] D28353: [X86] Optimize vector shifts with variable but uniform shift amounts

[Zvi Rackover via Phabricator via llvm-commits]

zvi created this revision.
zvi added reviewers: craig.topper, delena, RKSimon.
zvi added a subscriber: llvm-commits.
zvi set the repository for this revision to rL LLVM.

For instructions such as PSLLW/PSLLD/PSLLQ a variable shift amount may be passed in an XMM register.
The lower 64-bits of the register are evaluated to determine the shift amount.
This patch improves the construction of the vector containing the shift amount.


Repository:
  rL LLVM

https://reviews.llvm.org/D28353

Files:
  lib/Target/X86/X86ISelLowering.cpp
  test/CodeGen/X86/lower-vec-shift-2.ll
  test/CodeGen/X86/vector-rotate-128.ll
  test/CodeGen/X86/vector-shift-ashr-128.ll
  test/CodeGen/X86/vector-shift-ashr-256.ll
  test/CodeGen/X86/vector-shift-ashr-512.ll
  test/CodeGen/X86/vector-shift-lshr-128.ll
  test/CodeGen/X86/vector-shift-lshr-256.ll
  test/CodeGen/X86/vector-shift-lshr-512.ll
  test/CodeGen/X86/vector-shift-shl-128.ll
  test/CodeGen/X86/vector-shift-shl-256.ll
  test/CodeGen/X86/vector-shift-shl-512.ll
  test/CodeGen/X86/vshift-4.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D28353.83224.patch
Type: text/x-patch
Size: 35677 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20170105/9516b6af/attachment.bin>