[PATCH] D28087: X86 instr selection: combine ADDSUB + MUL to FMADDSUB

[Vyacheslav Klochkov via Phabricator via llvm-commits]

v_klochkov updated this revision to Diff 83206.
v_klochkov added a comment.

1. Made some restructures in ADDSUB idiom recognition. As a result of these changes 512-bit FMADDSUB idiom can be recognized and X86ISD::FMADDSUB is generated.

512-bit bit ADDSUB idiom can be recognized for float and double vectors now, but 512-bit X86ISD::ADDSUB is never generated because 512-bit ADDSUB instructions are not available in AVX512. The recognition of 512-bit ADDSUB is needed only as part of 512-bit FMADDSUB idiom recognition.

2. Updated the LIT test. Added 512-bit test cases to it. Also, made minor updates accordingly to Elena's suggestion.


https://reviews.llvm.org/D28087

Files:
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/test/CodeGen/X86/fmaddsub-combine.ll

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