[llvm] r291097 - [GlobalISel] Fix AArch64 ICMP instruction selection
Kristof Beyls via llvm-commits
llvm-commits at lists.llvm.org
Thu Jan 5 02:16:08 PST 2017
Author: kbeyls
Date: Thu Jan 5 04:16:08 2017
New Revision: 291097
URL: http://llvm.org/viewvc/llvm-project?rev=291097&view=rev
Log:
[GlobalISel] Fix AArch64 ICMP instruction selection
Differential Revision: https://reviews.llvm.org/D28175
Modified:
llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp
llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir
Modified: llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp?rev=291097&r1=291096&r2=291097&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp Thu Jan 5 04:16:08 2017
@@ -1071,8 +1071,12 @@ bool AArch64InstructionSelector::select(
return false;
}
- const AArch64CC::CondCode CC = changeICMPPredToAArch64CC(
- (CmpInst::Predicate)I.getOperand(1).getPredicate());
+ // CSINC increments the result by one when the condition code is false.
+ // Therefore, we have to invert the predicate to get an increment by 1 when
+ // the predicate is true.
+ const AArch64CC::CondCode invCC =
+ changeICMPPredToAArch64CC(CmpInst::getInversePredicate(
+ (CmpInst::Predicate)I.getOperand(1).getPredicate()));
MachineInstr &CmpMI = *BuildMI(MBB, I, I.getDebugLoc(), TII.get(CmpOpc))
.addDef(ZReg)
@@ -1084,7 +1088,7 @@ bool AArch64InstructionSelector::select(
.addDef(I.getOperand(0).getReg())
.addUse(AArch64::WZR)
.addUse(AArch64::WZR)
- .addImm(CC);
+ .addImm(invCC);
constrainSelectedInstRegOperands(CmpMI, TII, TRI, RBI);
constrainSelectedInstRegOperands(CSetMI, TII, TRI, RBI);
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir?rev=291097&r1=291096&r2=291097&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir Thu Jan 5 04:16:08 2017
@@ -2836,13 +2836,13 @@ registers:
# CHECK: body:
# CHECK: %wzr = SUBSWrr %0, %0, implicit-def %nzcv
-# CHECK: %1 = CSINCWr %wzr, %wzr, 0, implicit %nzcv
+# CHECK: %1 = CSINCWr %wzr, %wzr, 1, implicit %nzcv
# CHECK: %xzr = SUBSXrr %2, %2, implicit-def %nzcv
-# CHECK: %3 = CSINCWr %wzr, %wzr, 2, implicit %nzcv
+# CHECK: %3 = CSINCWr %wzr, %wzr, 3, implicit %nzcv
# CHECK: %xzr = SUBSXrr %4, %4, implicit-def %nzcv
-# CHECK: %5 = CSINCWr %wzr, %wzr, 1, implicit %nzcv
+# CHECK: %5 = CSINCWr %wzr, %wzr, 0, implicit %nzcv
body: |
bb.0:
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