[PATCH] D28099: AMDGPU: Fold fneg into fp_extend
Matt Arsenault via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Jan 3 08:36:44 PST 2017
arsenm retitled this revision from "DAGCombiner: Fold fneg into fp_extend if free" to "AMDGPU: Fold fneg into fp_extend ".
arsenm updated this revision to Diff 82893.
arsenm added a comment.
Herald added subscribers: tony-tye, yaxunl, kzhuravl.
Move into target
https://reviews.llvm.org/D28099
Files:
lib/Target/AMDGPU/AMDGPUISelLowering.cpp
test/CodeGen/AMDGPU/fneg-combines.ll
Index: test/CodeGen/AMDGPU/fneg-combines.ll
===================================================================
--- test/CodeGen/AMDGPU/fneg-combines.ll
+++ test/CodeGen/AMDGPU/fneg-combines.ll
@@ -655,6 +655,62 @@
ret void
}
+; --------------------------------------------------------------------------------
+; fp_extend tests
+; --------------------------------------------------------------------------------
+
+; GCN-LABEL: {{^}}v_fneg_fp_extend_f32_to_f64:
+; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
+; GCN: v_cvt_f64_f32_e64 [[RESULT:v\[[0-9]+:[0-9]+\]]], -[[A]]
+; GCN: buffer_store_dwordx2 [[RESULT]]
+define void @v_fneg_fp_extend_f32_to_f64(double addrspace(1)* %out, float addrspace(1)* %a.ptr) #0 {
+ %tid = call i32 @llvm.amdgcn.workitem.id.x()
+ %tid.ext = sext i32 %tid to i64
+ %a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext
+ %out.gep = getelementptr inbounds double, double addrspace(1)* %out, i64 %tid.ext
+ %a = load volatile float, float addrspace(1)* %a.gep
+ %fpext = fpext float %a to double
+ %fneg = fsub double -0.000000e+00, %fpext
+ store double %fneg, double addrspace(1)* %out.gep
+ ret void
+}
+
+; GCN-LABEL: {{^}}v_fneg_fp_extend_fneg_f32_to_f64:
+; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
+; GCN: v_cvt_f64_f32_e32 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[A]]
+; GCN: buffer_store_dwordx2 [[RESULT]]
+define void @v_fneg_fp_extend_fneg_f32_to_f64(double addrspace(1)* %out, float addrspace(1)* %a.ptr) #0 {
+ %tid = call i32 @llvm.amdgcn.workitem.id.x()
+ %tid.ext = sext i32 %tid to i64
+ %a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext
+ %out.gep = getelementptr inbounds double, double addrspace(1)* %out, i64 %tid.ext
+ %a = load volatile float, float addrspace(1)* %a.gep
+ %fneg.a = fsub float -0.000000e+00, %a
+ %fpext = fpext float %fneg.a to double
+ %fneg = fsub double -0.000000e+00, %fpext
+ store double %fneg, double addrspace(1)* %out.gep
+ ret void
+}
+
+; GCN-LABEL: {{^}}v_fneg_fp_extend_store_use_fneg_f32_to_f64:
+; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
+; GCN-DAG: v_cvt_f64_f32_e32 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[A]]
+; GCN-DAG: v_xor_b32_e32 [[FNEG_A:v[0-9]+]], 0x80000000, [[A]]
+; GCN: buffer_store_dwordx2 [[RESULT]]
+; GCN: buffer_store_dword [[FNEG_A]]
+define void @v_fneg_fp_extend_store_use_fneg_f32_to_f64(double addrspace(1)* %out, float addrspace(1)* %a.ptr) #0 {
+ %tid = call i32 @llvm.amdgcn.workitem.id.x()
+ %tid.ext = sext i32 %tid to i64
+ %a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext
+ %out.gep = getelementptr inbounds double, double addrspace(1)* %out, i64 %tid.ext
+ %a = load volatile float, float addrspace(1)* %a.gep
+ %fneg.a = fsub float -0.000000e+00, %a
+ %fpext = fpext float %fneg.a to double
+ %fneg = fsub double -0.000000e+00, %fpext
+ store volatile double %fneg, double addrspace(1)* %out.gep
+ store volatile float %fneg.a, float addrspace(1)* undef
+ ret void
+}
declare i32 @llvm.amdgcn.workitem.id.x() #1
declare float @llvm.fma.f32(float, float, float) #1
Index: lib/Target/AMDGPU/AMDGPUISelLowering.cpp
===================================================================
--- lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -2828,6 +2828,21 @@
DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res));
return Res;
}
+ case ISD::FP_EXTEND: {
+ SDValue CvtSrc = N0.getOperand(0);
+ if (CvtSrc.getOpcode() == ISD::FNEG) {
+ // (fneg (fp_extend (fneg x))) -> (fp_extend x)
+ return DAG.getNode(ISD::FP_EXTEND, SL, VT, CvtSrc.getOperand(0));
+ }
+
+ // (fneg (fp_extend x)) -> (fp_extend (fneg x))
+ //
+ // We want to fold negates through extends so they can be absorbed as
+ // modifiers, so we don't need the same conditions we have for folding
+ // through rounds.
+ SDValue Neg = DAG.getNode(ISD::FNEG, SL, CvtSrc.getValueType(), CvtSrc);
+ return DAG.getNode(ISD::FP_EXTEND, SL, VT, Neg);
+ }
default:
return SDValue();
}
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