[PATCH] D28087: X86 instr selection: combine ADDSUB + MUL to FMADDSUB

[Vyacheslav Klochkov via Phabricator via llvm-commits]

v_klochkov planned changes to this revision.
v_klochkov added a comment.

Elena,

I see my mistake now. CPU ISA says that ADDSUBPD/PS instructions are available for 128 and 256-bit vectors only.
It is not available for ZMMs.

So, if I want to make it possible to generate 512-bit F**M**ADDSUB instrutions, then I'll need to change a little bit the recognition of ADDSUB idioms, i.e. it should be possible to recognize ADDSUB, but never generate 512-bit X86ISD::ADDSUBs.

Thank you,
Vyacheslav Klochkov


https://reviews.llvm.org/D28087