[PATCH] D28198: [X86] Replace AND+IMM64 with SRL/SHL

[Nikolai Bozhenov via Phabricator via llvm-commits]

n.bozhenov created this revision.
n.bozhenov added reviewers: spatel, craig.topper, bkramer, jlebar.
n.bozhenov added subscribers: llvm-commits, zansari, DavidKreitzer, aaboud, volkalexey.

Emit SHRQ/SHLQ instead of ANDQ with a 64 bit constant mask if the result
is unused and the mask has only higher/lower bits set. For example, with
this patch LLVM emits

  shrq $41, %rdi
  je

instead of

  movabsq $0xFFFFFE0000000000, %rcx
  testq   %rcx, %rdi
  je

This reduces number of instructions, code size and register pressure.
The transformation is applied only for cases where the mask cannot be
encoded as an immediate value within TESTQ instruction.


https://reviews.llvm.org/D28198

Files:
  lib/Target/X86/X86ISelLowering.cpp
  test/CodeGen/X86/bypass-slow-division-64.ll
  test/CodeGen/X86/bypass-slow-division-tune.ll
  test/CodeGen/X86/cmp.ll

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