[llvm] r290778 - [AVR] Optimize 16-bit ANDs with '1'

[Dylan McKay via llvm-commits]

Author: dylanmckay
Date: Fri Dec 30 19:07:14 2016
New Revision: 290778

URL: http://llvm.org/viewvc/llvm-project?rev=290778&view=rev
Log:
[AVR]  Optimize 16-bit ANDs with '1'

Summary: Fixes PR 31345

Reviewers: dylanmckay

Subscribers: fhahn, llvm-commits

Differential Revision: https://reviews.llvm.org/D28186

Added:
    llvm/trunk/test/CodeGen/AVR/PR31345.ll
Modified:
    llvm/trunk/lib/Target/AVR/AVRExpandPseudoInsts.cpp
    llvm/trunk/test/CodeGen/AVR/and.ll

Modified: llvm/trunk/lib/Target/AVR/AVRExpandPseudoInsts.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AVR/AVRExpandPseudoInsts.cpp?rev=290778&r1=290777&r2=290778&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AVR/AVRExpandPseudoInsts.cpp (original)
+++ llvm/trunk/lib/Target/AVR/AVRExpandPseudoInsts.cpp Fri Dec 30 19:07:14 2016
@@ -203,6 +203,10 @@ expandLogic(unsigned Op, Block &MBB, Blo
 bool AVRExpandPseudo::
   isLogicImmOpRedundant(unsigned Op, unsigned ImmVal) const {
 
+  // ANDI Rd, 0xff is redundant.
+  if (Op == AVR::ANDIRdK && ImmVal == 0xff)
+    return true;
+
   // ORI Rd, 0x0 is redundant.
   if (Op == AVR::ORIRdK && ImmVal == 0x0)
     return true;

Added: llvm/trunk/test/CodeGen/AVR/PR31345.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/PR31345.ll?rev=290778&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/PR31345.ll (added)
+++ llvm/trunk/test/CodeGen/AVR/PR31345.ll Fri Dec 30 19:07:14 2016
@@ -0,0 +1,51 @@
+; RUN: llc < %s -march=avr | FileCheck %s
+
+; Unit test for: PR 31345
+
+define i16 @and16_reg_imm_0xff00(i16 %a) {
+; CHECK-LABEL: and16_reg_imm_0xff00
+; CHECK: andi {{r[0-9]+}}, 0
+; CHECK-NOT: andi {{r[0-9]+}}, 255
+    %result = and i16 %a, 65280
+    ret i16 %result
+}
+
+define i16 @and16_reg_imm_0xffb3(i16 %a) {
+; CHECK-LABEL: and16_reg_imm_0xffb3
+; CHECK: andi {{r[0-9]+}}, 179
+; CHECK-NOT: andi {{r[0-9]+}}, 255
+    %result = and i16 %a, 65459
+    ret i16 %result
+}
+
+define i16 @and16_reg_imm_0x00ff(i16 %a) {
+; CHECK-LABEL: and16_reg_imm_0x00ff
+; CHECK-NOT: andi {{r[0-9]+}}, 255
+; CHECK: andi {{r[0-9]+}}, 0
+    %result = and i16 %a, 255
+    ret i16 %result
+}
+
+define i16 @and16_reg_imm_0xb3ff(i16 %a) {
+; CHECK-LABEL: and16_reg_imm_0xb3ff
+; CHECK-NOT: andi {{r[0-9]+}}, 255
+; CHECK: andi {{r[0-9]+}}, 179
+    %result = and i16 %a, 46079
+    ret i16 %result
+}
+
+define i16 @and16_reg_imm_0xffff(i16 %a) {
+; CHECK-LABEL: and16_reg_imm_0xffff
+; CHECK-NOT: andi {{r[0-9]+}}, 255
+; CHECK-NOT: andi {{r[0-9]+}}, 255
+    %result = and i16 %a, 65535
+    ret i16 %result
+}
+
+define i16 @and16_reg_imm_0xabcd(i16 %a) {
+; CHECK-LABEL: and16_reg_imm_0xabcd
+; CHECK: andi {{r[0-9]+}}, 205
+; CHECK: andi {{r[0-9]+}}, 171
+    %result = and i16 %a, 43981
+    ret i16 %result
+}

Modified: llvm/trunk/test/CodeGen/AVR/and.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/and.ll?rev=290778&r1=290777&r2=290778&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/and.ll (original)
+++ llvm/trunk/test/CodeGen/AVR/and.ll Fri Dec 30 19:07:14 2016
@@ -67,7 +67,8 @@ define i64 @and64_reg_reg(i64 %a, i64 %b
 define i64 @and64_reg_imm(i64 %a) {
 ; CHECK-LABEL: and64_reg_imm:
 ; CHECK: andi r18, 253
-; CHECK: andi r19, 255
+; Per PR 31345, we optimize away ANDI Rd, 0xff
+; CHECK-NOT: andi r19, 255
 ; CHECK: andi r20, 155
 ; CHECK: andi r21, 88
 ; CHECK: andi r22, 76