[PATCH] D28159: [ARM] Fix test CodeGen/ARM/fpcmp_ueq.ll broken by rL290616

[Evgeny Astigeevich via Phabricator via llvm-commits]

eastig created this revision.
eastig added reviewers: rengolin, t.p.northover.
eastig added subscribers: llvm-commits, compnerd.
Herald added a subscriber: aemerson.

Commit https://reviews.llvm.org/rL290616 (https://reviews.llvm.org/rL290616) changed a checking command for the triple arm-apple-darwin in LLVM::CodeGen/ARM/fpcmp_ueq.ll from

  RUN: llc < %s -mtriple=arm-apple-darwin | grep moveq 

to

  RUN: llc -mtriple arm-apple-darwin -filetype asm -o - %s | FileCheck -check-prefix CHECK-ARMv4 %s

It also added the following checks:

  ; CHECK-ARMv4-LABEL: f7:
  ; CHECK-ARMv4: moveq r6, #1
  ; CHECK-ARMv4: moveq r0, #42

These changes introduced a sequence of instructions to be checked. Before the changes it was expected any number of moveq. Now it is expected two concrete moveq.

The tested code is:

  define i32 @f7(float %a, float %b) {
  entry:
    %tmp = fcmp ueq float %a,%b
    %retval = select i1 %tmp, i32 666, i32 42
    ret i32 %retval
  }

For the triple 'arm-apple-darwin' the generated code is:

          .section        __TEXT,__text,regular,pure_instructions
          .syntax unified
          .globl  _f7
          .p2align        2
          .code   32                      @ @f7
  _f7:
  @ BB#0:                                 @ %entry
          push    {r4, r5, r6, lr}
          mov     r4, r1
          mov     r5, r0
          bl      ___eqsf2
          cmp     r0, #0
          mov     r6, #0
          mov     r0, r5
          mov     r1, r4
          moveq   r6, #1
          bl      ___unordsf2
          cmp     r0, #0
          movne   r0, #1
          orrs    r0, r0, r6
          mov     r0, #154
          orr     r0, r0, #512
          moveq   r0, #42
          pop     {r4, r5, r6, lr}
          mov     pc, lr
   
  .subsections_via_symbols

The final result depends on results of ___eqsf2 and ___unordsf2. 'r6' is used to keep a value based on a result of ___eqsf2. First, the name of the register is not fixed. Second, the value in 'r6' can be constructed without using moveq.

The patch introduces another sequence of instructions to be checked:

  ; CHECK-ARMv4-LABEL: f7:
  ; CHECK-ARMv4: bl
  ; CHECK-ARMv4: bl
  ; CHECK-ARMv4: cmp r0, #0
  ; CHECK-ARMv4: movne r0, #1
  ; CHECK-ARMv4: orrs r0, r0,
  ; CHECK-ARMv4: moveq r0, #42

It means there are calls of some functions then their results are combined and the final result in 'r0' is based on the combined result.


https://reviews.llvm.org/D28159

Files:
  test/CodeGen/ARM/fpcmp_ueq.ll


Index: test/CodeGen/ARM/fpcmp_ueq.ll
===================================================================
--- test/CodeGen/ARM/fpcmp_ueq.ll
+++ test/CodeGen/ARM/fpcmp_ueq.ll
@@ -9,7 +9,11 @@
 }
 
 ; CHECK-ARMv4-LABEL: f7:
-; CHECK-ARMv4: moveq r6, #1
+; CHECK-ARMv4: bl
+; CHECK-ARMv4: bl
+; CHECK-ARMv4: cmp r0, #0
+; CHECK-ARMv4: movne r0, #1
+; CHECK-ARMv4: orrs r0, r0,
 ; CHECK-ARMv4: moveq r0, #42
 
 ; CHECK-ARMv7-LABEL: f7:


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D28159.82671.patch
Type: text/x-patch
Size: 431 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20161229/1f493e99/attachment.bin>