[PATCH] D28122: RuntimeDyldELF: implement R_AARCH64_PREL64 reloc

[Eugene Leviant via Phabricator via llvm-commits]

evgeny777 updated this revision to Diff 82657.
evgeny777 added a comment.

I've added BE test for PREL64 and BE/LE tests for PREL32 (feature was there already, but wasn't tested)

So currently supported AArch64 relocs are:
ABS64: LE/BE
ABS32: LE/BE
PREL32: LE/BE
PREL64: LE/BE
CALL26/JUMP26 : LE
MOVW_UABS_G3: LE (BE test is incorrect: it passes, but checks for invalid values)
MOVW_UABS_G2_NC: LE (BE test is incorrect: it passes, but checks for invalid values)
MOVW_UABS_G1_NC: LE (BE test is incorrect: it passes, but checks for invalid values)
MOVW_UABS_G0_NC: LE (BE test is incorrect: it passes, but checks for invalid values)
PREL_PG_HI21: LE (not tested)
ADD_ABS_LO12_NC: LE
LDST32_ABS_LO12_NC: LE (not tested)
LDST64_ABS_LO12_NC: LE (not tested)

Hope this helps


https://reviews.llvm.org/D28122

Files:
  lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp
  test/ExecutionEngine/RuntimeDyld/AArch64/ELF_ARM64_BE-relocations.s
  test/ExecutionEngine/RuntimeDyld/AArch64/ELF_ARM64_relocations.s


Index: test/ExecutionEngine/RuntimeDyld/AArch64/ELF_ARM64_relocations.s
===================================================================
--- test/ExecutionEngine/RuntimeDyld/AArch64/ELF_ARM64_relocations.s
+++ test/ExecutionEngine/RuntimeDyld/AArch64/ELF_ARM64_relocations.s
@@ -1,6 +1,11 @@
 # RUN: llvm-mc -triple=arm64-none-linux-gnu -filetype=obj -o %T/reloc.o %s
 # RUN: llvm-rtdyld -triple=arm64-none-linux-gnu -verify -dummy-extern f=0x0123456789abcdef -check=%s %T/reloc.o
-
+        
+        .globl Q
+        .section .dummy, "ax"
+Q:
+        nop
+          
         .text
         .globl  g
         .p2align        2
@@ -27,13 +32,20 @@
         .p2align        3
 k:
         .xword  f
-        .size   k, 8
+        .size   k, 16
+r:
+# R_AARCH64_PREL64
+        .xword  f - .
+# R_AARCH64_PREL32: use Q instead of f to fit in 32 bits.
+        .word  Q - .
 
 # rtdyld-check: *{4}(g) = 0xd2e02460
 # rtdyld-check: *{4}(g + 4) = 0xf2c8ace0
 # rtdyld-check: *{4}(g + 8) = 0xf2b13560
 # rtdyld-check: *{4}(g + 12) = 0xf299bde0
 # rtdyld-check: *{8}k = f
+# rtdyld-check: *{8}(r) = f - r
+# rtdyld-check: *{4}(r + 8) = (Q - r - 8)[31:0]
 
 ## f & 0xFFF = 0xdef (bits 11:0 of f)
 ## 0xdef << 10 = 0x37bc00
Index: test/ExecutionEngine/RuntimeDyld/AArch64/ELF_ARM64_BE-relocations.s
===================================================================
--- test/ExecutionEngine/RuntimeDyld/AArch64/ELF_ARM64_BE-relocations.s
+++ test/ExecutionEngine/RuntimeDyld/AArch64/ELF_ARM64_BE-relocations.s
@@ -1,6 +1,11 @@
 # RUN: llvm-mc -triple=aarch64_be-none-linux-gnu -filetype=obj -o %T/be-reloc.o %s
 # RUN: llvm-rtdyld -triple=aarch64_be-none-linux-gnu -verify -dummy-extern f=0x0123456789abcdef -check=%s %T/be-reloc.o
 
+        .globl Q
+        .section .dummy, "ax"
+Q:
+        nop
+
         .text
         .globl  g
         .p2align        2
@@ -23,12 +28,19 @@
         .globl  k
         .p2align        3
 k:
-        .xword  f
+        .xword  f        
         .size   k, 8
+r:
+# R_AARCH64_PREL64
+        .xword  f - .
+# R_AARCH64_PREL32: use Q instead of f to fit in 32 bits.
+        .word  Q - .
 
 # LE instructions read as BE
 # rtdyld-check: *{4}(g) = 0x6024e0d2
 # rtdyld-check: *{4}(g + 4) = 0xe0acc8f2
 # rtdyld-check: *{4}(g + 8) = 0x6035b1f2
 # rtdyld-check: *{4}(g + 12) = 0xe0bd99f2
 # rtdyld-check: *{8}k = f
+# rtdyld-check: *{8}(r) = f - r
+# rtdyld-check: *{4}(r + 8) = (Q - r - 8)[31:0]
Index: lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp
===================================================================
--- lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp
+++ lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp
@@ -374,6 +374,9 @@
     write(isBE, TargetPtr, static_cast<uint32_t>(Result & 0xffffffffU));
     break;
   }
+  case ELF::R_AARCH64_PREL64:
+    write(isBE, TargetPtr, Value + Addend - FinalAddress);
+    break;
   case ELF::R_AARCH64_CALL26: // fallthrough
   case ELF::R_AARCH64_JUMP26: {
     // Operation: S+A-P. Set Call or B immediate value to bits fff_fffc of the


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