[PATCH] D28135: SelectionDAG: Fix in legalization of UMAX/SMAX/UMIN/SMIN. Solves PR31486.

[Mikael Holmén via Phabricator via llvm-commits]

uabelho retitled this revision from "    SelectionDAG: Fix in legalization of UMAX/SMAX/UMIN/SMIN. Solves PR31486." to "SelectionDAG: Fix in legalization of UMAX/SMAX/UMIN/SMIN. Solves PR31486.".
uabelho updated the summary for this revision.
uabelho updated this revision to Diff 82651.
uabelho added a comment.
Herald added a subscriber: wdng.

Updated the test case.


https://reviews.llvm.org/D28135

Files:
  lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
  test/CodeGen/AMDGPU/legalize-umax-bug.ll


Index: test/CodeGen/AMDGPU/legalize-umax-bug.ll
===================================================================
--- /dev/null
+++ test/CodeGen/AMDGPU/legalize-umax-bug.ll
@@ -0,0 +1,18 @@
+; RUN: llc -march=r600 -mcpu=cypress -start-after safe-stack %s -o /dev/null
+; Don't crash
+
+target datalayout = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
+target triple = "r600--"
+
+define void @test(i64 addrspace(1)* %out) {
+bb:
+  store i64 2, i64 addrspace(1)* %out
+  %tmp = load i64, i64 addrspace(1)* %out
+  br label %jump
+
+jump:                                             ; preds = %bb
+  %tmp1 = icmp ugt i64 %tmp, 4
+  %umax = select i1 %tmp1, i64 %tmp, i64 4
+  store i64 %umax, i64 addrspace(1)* %out
+  ret void
+}
Index: lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -1710,7 +1710,7 @@
   EVT CCT = getSetCCResultType(NVT);
 
   // Hi part is always the same op
-  Hi = DAG.getNode(N->getOpcode(), DL, {NVT, NVT}, {LHSH, RHSH});
+  Hi = DAG.getNode(N->getOpcode(), DL, NVT, {LHSH, RHSH});
 
   // We need to know whether to select Lo part that corresponds to 'winning'
   // Hi part or if Hi parts are equal.
@@ -1721,7 +1721,7 @@
   SDValue LoCmp = DAG.getSelect(DL, NVT, IsHiLeft, LHSL, RHSL);
 
   // Recursed Lo part if Hi parts are equal, this uses unsigned version
-  SDValue LoMinMax = DAG.getNode(LoOpc, DL, {NVT, NVT}, {LHSL, RHSL});
+  SDValue LoMinMax = DAG.getNode(LoOpc, DL, NVT, {LHSL, RHSL});
 
   Lo = DAG.getSelect(DL, NVT, IsHiEq, LoMinMax, LoCmp);
 }


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