[PATCH] D27990: [Thumb] Add support for tMUL in the compare instruction peephole optimizer

[Sjoerd Meijer via Phabricator via llvm-commits]

SjoerdMeijer added a comment.

Hi Diana,

Thanks a lot for the review! We are generating these constants and moves for an expression like "return A*B == C", where A and B are variables and C is a constant, because this is lowered involving a select_cc is generated. For example:

  %mul = mul nsw i32 %b, %a
  %cmp = icmp eq i32 %mul, 0
  %conv = zext i1 %cmp to i32
  ret i32 %conv

this IR gets instruction selected to:

t5: i32 = mul t4, t2

      t19: glue = ARMISD::CMPZ t5, Constant:i32<0>
    t20: i32 = ARMISD::CMOV Constant:i32<0>, Constant:i32<1>, Constant:i32<0>, Register:i32 %CPSR, t19
  t11: ch,glue = CopyToReg t0, Register:i32 %R0, t20
  t12: ch = ARMISD::RET_FLAG t11, Register:i32 %R0, t11:1

and then we end up with these MIs:

%vreg2<def,tied3>, %CPSR<def> = tMUL %vreg1, %vreg0<tied0>, pred:14, pred:%noreg; tGPR:%vreg2,%vreg1,%vreg0

  %vreg3<def>, %CPSR<def> = tMOVi8 1, pred:14, pred:%noreg; tGPR:%vreg3
  %vreg4<def>, %CPSR<def> = tMOVi8 0, pred:14, pred:%noreg; tGPR:%vreg4
  tCMPi8 %vreg2<kill>, 0, pred:14, pred:%noreg, %CPSR<imp-def>; tGPR:%vreg2
  %vreg5<def> = tMOVCCr_pseudo %vreg4<kill>, %vreg3<kill>, pred:0, pred:%CPSR; tGPR:%vreg5,%vreg4,%vreg3
  %R0<def> = COPY %vreg5; tGPR:%vreg5
  tBX_RET

And the issue is that the move immediate instruction for Thumb1 (V6M) updates the condition flags.

The elegant solution would be a bit of (early) CFG restructuring and 2 exit blocks return the true/false conditions, so that we end up with something similar to this:

  MULS     r0,r1,r0
  BEQ      |L0.8|
  MOVS     r0,#0
  BX       lr

| L0.8 |

  MOVS     r0,#1
  BX       lr

But to achieve that at this point is difficult, hence my solution to simply reorder the constants and the operation.


https://reviews.llvm.org/D27990