[llvm] r290380 - [MachineVerifier] Check that even generic vregs comply to regclass constraints.

[Quentin Colombet via llvm-commits]

Author: qcolombet
Date: Thu Dec 22 15:56:39 2016
New Revision: 290380

URL: http://llvm.org/viewvc/llvm-project?rev=290380&view=rev
Log:
[MachineVerifier] Check that even generic vregs comply to regclass constraints.

We used to not check generic vregs, but that is actually a mistake given
nothing in the GlobalISel pipeline is going to fix the constraints on
target specific instructions. Therefore, the target has to have them
right from the start.

Modified:
    llvm/trunk/lib/CodeGen/MachineVerifier.cpp

Modified: llvm/trunk/lib/CodeGen/MachineVerifier.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineVerifier.cpp?rev=290380&r1=290379&r2=290380&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineVerifier.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineVerifier.cpp Thu Dec 22 15:56:39 2016
@@ -1056,6 +1056,21 @@ MachineVerifier::visitMachineOperand(con
                    MONum);
             return;
           }
+
+          // If this is a target specific instruction and this operand
+          // has register class constraint, the virtual register must
+          // comply to it.
+          if (!isPreISelGenericOpcode(MCID.getOpcode()) &&
+              TII->getRegClass(MCID, MONum, TRI, *MF)) {
+            report("Virtual register does not match instruction constraint", MO,
+                   MONum);
+            errs() << "Expect register class "
+                   << TRI->getRegClassName(
+                          TII->getRegClass(MCID, MONum, TRI, *MF))
+                   << " but got nothing\n";
+            return;
+          }
+
           break;
         }
         if (SubIdx) {