[llvm] r290375 - [RegisterBankInfo] Allow to set a register class when nothing else is set

[Quentin Colombet via llvm-commits]

Author: qcolombet
Date: Thu Dec 22 15:56:26 2016
New Revision: 290375

URL: http://llvm.org/viewvc/llvm-project?rev=290375&view=rev
Log:
[RegisterBankInfo] Allow to set a register class when nothing else is set

This is going to be needed to be able to constraint register class on
target specific instruction while the RegBankSelect pass did not run
yet.

Modified:
    llvm/trunk/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp

Modified: llvm/trunk/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp?rev=290375&r1=290374&r2=290375&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp (original)
+++ llvm/trunk/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp Thu Dec 22 15:56:26 2016
@@ -224,12 +224,11 @@ const TargetRegisterClass *RegisterBankI
     return MRI.constrainRegClass(Reg, &RC);
 
   const RegisterBank *RB = RegClassOrBank.get<const RegisterBank *>();
-  assert(RB && "Generic register does not have a register bank");
-
   // Otherwise, all we can do is ensure the bank covers the class, and set it.
-  if (!RB->covers(RC))
+  if (RB && !RB->covers(RC))
     return nullptr;
 
+  // If nothing was set or the class is simply compatible, set it.
   MRI.setRegClass(Reg, &RC);
   return &RC;
 }