[PATCH] D27856: [mips] Compact branch hazard detection

[Petar Jovanovic via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL290361: [mips] Fix compact branch hazard detection, part 2 (authored by petarj).

Changed prior to commit:
  https://reviews.llvm.org/D27856?vs=81771&id=82355#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D27856

Files:
  llvm/trunk/lib/Target/Mips/MipsHazardSchedule.cpp
  llvm/trunk/test/CodeGen/Mips/compactbranches/unsafe-in-forbidden-slot.ll


Index: llvm/trunk/lib/Target/Mips/MipsHazardSchedule.cpp
===================================================================
--- llvm/trunk/lib/Target/Mips/MipsHazardSchedule.cpp
+++ llvm/trunk/lib/Target/Mips/MipsHazardSchedule.cpp
@@ -103,24 +103,23 @@
 
 // Find the next real instruction from the current position, looking through
 // basic block boundaries.
-static Iter getNextMachineInstr(Iter Position) {
-  if (std::next(Position) == Position->getParent()->end()) {
-    const MachineBasicBlock * MBB = (&*Position)->getParent();
-    for (auto *Succ : MBB->successors()) {
-      if (MBB->isLayoutSuccessor(Succ)) {
-        Iter I = Succ->begin();
-        Iter Next = getNextMachineInstrInBB(I);
-        if (Next == Succ->end()) {
-          return getNextMachineInstr(I);
-        } else {
-          return I;
-        }
-      }
+static Iter getNextMachineInstr(Iter Position, MachineBasicBlock *Parent) {
+  if (Position == Parent->end()) {
+    MachineBasicBlock *Succ = Parent->getNextNode();
+    if (Succ != nullptr && Parent->isSuccessor(Succ)) {
+      Position = Succ->begin();
+      Parent = Succ;
+    } else {
+      llvm_unreachable(
+          "Should have identified the end of the function earlier!");
     }
-    llvm_unreachable("Should have identified the end of the function earlier!");
   }
 
-  return getNextMachineInstrInBB(Position);
+  Iter Instr = getNextMachineInstrInBB(Position);
+  if (Instr == Parent->end()) {
+    return getNextMachineInstr(Instr, Parent);
+  }
+  return Instr;
 }
 
 bool MipsHazardSchedule::runOnMachineFunction(MachineFunction &MF) {
@@ -146,13 +145,7 @@
       bool LastInstInFunction =
           std::next(I) == FI->end() && std::next(FI) == MF.end();
       if (!LastInstInFunction) {
-        if (std::next(I) != FI->end()) {
-          // Start looking from the next instruction in the basic block.
-          Inst = getNextMachineInstr(std::next(I));
-        } else {
-          // Next instruction in the physical successor basic block.
-          Inst = getNextMachineInstr(I);
-        }
+        Inst = getNextMachineInstr(std::next(I), &*FI);
       }
 
       if (LastInstInFunction || !TII->SafeInForbiddenSlot(*Inst)) {
Index: llvm/trunk/test/CodeGen/Mips/compactbranches/unsafe-in-forbidden-slot.ll
===================================================================
--- llvm/trunk/test/CodeGen/Mips/compactbranches/unsafe-in-forbidden-slot.ll
+++ llvm/trunk/test/CodeGen/Mips/compactbranches/unsafe-in-forbidden-slot.ll
@@ -0,0 +1,34 @@
+; RUN: llc -march=mips64el -O0 -mcpu=mips64r6 < %s | FileCheck %s
+; RUN: llc -march=mips64 -O0 -mcpu=mips64r6 < %s | FileCheck %s
+
+ at boo = global i32 0, align 4
+
+; Function Attrs: nounwind
+define void @_Z3foov() #0 {
+entry:
+  %0 = load volatile i32, i32* @boo, align 4
+  switch i32 %0, label %sw.epilog [
+    i32 0, label %sw.bb
+    i32 1, label %sw.bb1
+    i32 2, label %sw.bb1
+  ]
+
+sw.bb:                                            ; preds = %entry
+  store volatile i32 1, i32* @boo, align 4
+  br label %sw.epilog
+; CHECK: beqzc
+; CHECK-NEXT: nop
+; CHECK-NEXT: .LBB
+; CHECK-NEXT: j
+
+sw.bb1:                                           ; preds = %entry, %entry
+  store volatile i32 2, i32* @boo, align 4
+  br label %sw.epilog
+; CHECK: bnezc
+; CHECK-NEXT: nop
+; CHECK-NEXT: .LBB
+; CHECK-NEXT: j
+
+sw.epilog:                                        ; preds = %entry, %sw.bb1, %sw.bb
+  ret void
+}


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