[llvm] r290324 - Fix an assertion in DwarfExpression when emitting fragments in vector registers
Adrian Prantl via llvm-commits
llvm-commits at lists.llvm.org
Wed Dec 21 22:10:41 PST 2016
Author: adrian
Date: Thu Dec 22 00:10:41 2016
New Revision: 290324
URL: http://llvm.org/viewvc/llvm-project?rev=290324&view=rev
Log:
Fix an assertion in DwarfExpression when emitting fragments in vector registers
When DwarfExpression is emitting a fragment that is located in a
register and that fragment is smaller than the register, and the
register must be composed from sub-registers (are you still with me?)
the last DW_OP_piece operation must not be larger than the size of the
fragment itself, since the last piece of the fragment could be smaller
than the last subregister that is being emitted.
rdar://problem/29779065
Added:
llvm/trunk/test/DebugInfo/ARM/partial-subreg.ll
Modified:
llvm/trunk/lib/CodeGen/AsmPrinter/DwarfExpression.cpp
llvm/trunk/lib/CodeGen/AsmPrinter/DwarfExpression.h
Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfExpression.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfExpression.cpp?rev=290324&r1=290323&r2=290324&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfExpression.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfExpression.cpp Thu Dec 22 00:10:41 2016
@@ -86,7 +86,7 @@ bool DwarfExpression::AddMachineRegIndir
}
bool DwarfExpression::AddMachineReg(const TargetRegisterInfo &TRI,
- unsigned MachineReg) {
+ unsigned MachineReg, unsigned MaxSize) {
if (!TRI.isPhysicalRegister(MachineReg))
return false;
@@ -137,10 +137,12 @@ bool DwarfExpression::AddMachineReg(cons
// its range, emit a DWARF piece for it.
if (Reg >= 0 && Intersection.any()) {
AddReg(Reg, "sub-register");
+ if (Offset >= MaxSize)
+ break;
// Emit a piece for the any gap in the coverage.
if (Offset > CurPos)
AddOpPiece(Offset - CurPos);
- AddOpPiece(Size);
+ AddOpPiece(std::min<unsigned>(Size, MaxSize - Offset));
CurPos = Offset + Size;
// Mark it as emitted.
@@ -196,9 +198,12 @@ bool DwarfExpression::AddMachineRegExpre
bool ValidReg = false;
auto Op = ExprCursor.peek();
switch (Op->getOp()) {
- default:
- ValidReg = AddMachineReg(TRI, MachineReg);
+ default: {
+ auto Fragment = ExprCursor.getFragmentInfo();
+ ValidReg = AddMachineReg(TRI, MachineReg,
+ Fragment ? Fragment->SizeInBits : ~1U);
break;
+ }
case dwarf::DW_OP_plus:
case dwarf::DW_OP_minus: {
// [DW_OP_reg,Offset,DW_OP_plus, DW_OP_deref] --> [DW_OP_breg, Offset].
Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfExpression.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfExpression.h?rev=290324&r1=290323&r2=290324&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfExpression.h (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfExpression.h Thu Dec 22 00:10:41 2016
@@ -72,6 +72,11 @@ public:
}
/// Determine whether there are any operations left in this expression.
operator bool() const { return Start != End; }
+
+ /// Retrieve the fragment information, if any.
+ Optional<DIExpression::FragmentInfo> getFragmentInfo() const {
+ return DIExpression::getFragmentInfo(Start, End);
+ }
};
/// Base class containing the logic for constructing DWARF expressions
@@ -145,6 +150,10 @@ public:
/// Emit a partial DWARF register operation.
///
/// \param MachineReg The register number.
+ /// \param MaxSize If the register must be composed from
+ /// sub-registers this is an upper bound
+ /// for how many bits the emitted DW_OP_piece
+ /// may cover.
///
/// If size and offset is zero an operation for the entire register is
/// emitted: Some targets do not provide a DWARF register number for every
@@ -153,7 +162,8 @@ public:
/// multiple subregisters that alias the register.
///
/// \return false if no DWARF register exists for MachineReg.
- bool AddMachineReg(const TargetRegisterInfo &TRI, unsigned MachineReg);
+ bool AddMachineReg(const TargetRegisterInfo &TRI, unsigned MachineReg,
+ unsigned MaxSize = ~1U);
/// Emit a signed constant.
void AddSignedConstant(int64_t Value);
Added: llvm/trunk/test/DebugInfo/ARM/partial-subreg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/ARM/partial-subreg.ll?rev=290324&view=auto
==============================================================================
--- llvm/trunk/test/DebugInfo/ARM/partial-subreg.ll (added)
+++ llvm/trunk/test/DebugInfo/ARM/partial-subreg.ll Thu Dec 22 00:10:41 2016
@@ -0,0 +1,66 @@
+; RUN: llc %s -filetype=obj -o - | llvm-dwarfdump - | FileCheck %s
+; This tests a fragment that partially covers subregister compositions.
+;
+; Our fragment is 96 bits long and lies in a 128-bit register, which
+; in turn has to be composed out of its two 64-bit subregisters.
+
+; CHECK: .debug_info
+; CHECK: DW_TAG_subprogram
+; CHECK: DW_AT_name {{.*}}"subscript.get"
+; CHECK: DW_TAG_formal_parameter
+; CHECK-NEXT: DW_AT_location [DW_FORM_sec_offset] (0x00000000)
+; CHECK: .debug_loc
+; CHECK: 0x00000000: Beginning address offset
+; CHECK-NEXT: Ending address offset
+; CHECK-NEXT: Location description: 90 90 02 93 08 90 91 02 93 04
+; d16, piece 0x00000008, d17, piece 0x00000004
+source_filename = "simd.ll"
+target datalayout = "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
+target triple = "armv7-apple-ios7.0"
+
+; Function Attrs: nounwind readnone
+declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #0
+
+define <3 x float> @_TFV4simd8float2x3g9subscriptFSiVS_6float3(i32, <3 x float>, <3 x float>) !dbg !5 {
+entry:
+ tail call void @llvm.dbg.value(metadata <3 x float> %1, i64 0, metadata !8, metadata !9), !dbg !10
+ tail call void @llvm.dbg.value(metadata <3 x float> %2, i64 0, metadata !8, metadata !11), !dbg !10
+ %3 = icmp eq i32 %0, 0, !dbg !12
+ br i1 %3, label %7, label %4, !dbg !12
+
+; <label>:4: ; preds = %entry
+ %5 = icmp eq i32 %0, 1, !dbg !15
+ br i1 %5, label %7, label %6, !dbg !15
+
+; <label>:6: ; preds = %4
+ unreachable, !dbg !17
+
+; <label>:7: ; preds = %4, %entry
+ %8 = phi <3 x float> [ %1, %entry ], [ %2, %4 ], !dbg !18
+ ret <3 x float> %8, !dbg !18
+}
+
+attributes #0 = { nounwind readnone }
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!3, !4}
+
+!0 = distinct !DICompileUnit(language: DW_LANG_Swift, file: !1, producer: "Swift", isOptimized: false, runtimeVersion: 3, emissionKind: FullDebug, enums: !2, imports: !2)
+!1 = !DIFile(filename: "simd.swift", directory: "/")
+!2 = !{}
+!3 = !{i32 2, !"Dwarf Version", i32 4}
+!4 = !{i32 2, !"Debug Info Version", i32 3}
+!5 = distinct !DISubprogram(name: "subscript.get", linkageName: "_TFV4simd8float2x3g9subscriptFSiVS_6float3", scope: !6, file: !1, type: !7, isLocal: false, isDefinition: true, isOptimized: true, unit: !0, variables: !2)
+!6 = !DICompositeType(tag: DW_TAG_structure_type, name: "float2x3", scope: !0, file: !1, line: 5824, size: 256, align: 128, elements: !2, runtimeLang: DW_LANG_Swift, identifier: "_TtV4simd8float2x3")
+!7 = !DISubroutineType(types: !2)
+!8 = !DILocalVariable(name: "self", arg: 2, scope: !5, file: !1, line: 5897, type: !6, flags: DIFlagArtificial)
+!9 = !DIExpression(DW_OP_LLVM_fragment, 0, 96)
+!10 = !DILocation(line: 5897, column: 5, scope: !5)
+!11 = !DIExpression(DW_OP_LLVM_fragment, 96, 96)
+!12 = !DILocation(line: 5900, column: 12, scope: !13)
+!13 = distinct !DILexicalBlock(scope: !14, file: !1, line: 5898, column: 7)
+!14 = distinct !DILexicalBlock(scope: !5, file: !1, line: 5897, column: 9)
+!15 = !DILocation(line: 5902, column: 12, scope: !16)
+!16 = distinct !DILexicalBlock(scope: !14, file: !1, line: 5898, column: 7)
+!17 = !DILocation(line: 0, scope: !5)
+!18 = !DILocation(line: 5906, column: 5, scope: !14)
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