[PATCH] D28017: AMD family 17h (znver1) enablement

[Ganesh Gopalasubramanian via Phabricator via llvm-commits]

GGanesh created this revision.
GGanesh added a reviewer: craig.topper.
GGanesh added a subscriber: llvm-commits.
GGanesh set the repository for this revision to rL LLVM.

This patch enables the following

1. AMD family 17h architecture using "znver1" tune flag (-march, -mcpu).
2. ISAs that are enabled for "znver1" architecture.
3. Checks ADX isa from cpuid to identify "znver1" flag when -march=native is used.
4. Enables CLZERO feature and adds the builtin macro __builtin_ia32_clzero for clzero instruction.
5. ISAs FMA4, XOP are disabled as they are dropped from amdfam17.
6. For the time being, it uses the btver2 scheduler model.
7. Test file is updated to check this flag.


Repository:
  rL LLVM

https://reviews.llvm.org/D28017

Files:
  include/llvm/IR/IntrinsicsX86.td
  lib/Support/Host.cpp
  lib/Target/X86/X86.td
  lib/Target/X86/X86InstrInfo.td
  lib/Target/X86/X86Schedule.td
  lib/Target/X86/X86Subtarget.cpp
  lib/Target/X86/X86Subtarget.h
  test/CodeGen/X86/cpus.ll

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