[PATCH] D27916: [RFC]Make the canonicalisation on shifts benifit to more case.

[jojo.ma via Phabricator via llvm-commits]

jojo updated this revision to Diff 82198.
jojo added a comment.

1. Change according to inline comments
2. Create tests for this change on ARM
3. Some changes on the check line of Thumb2/machine-licm.ll, new canonicalisation will lead the tests to different instructions sequence.


https://reviews.llvm.org/D27916

Files:
  lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  test/CodeGen/ARM/shift-combine.ll
  test/CodeGen/Thumb2/machine-licm.ll


Index: test/CodeGen/ARM/shift-combine.ll
===================================================================
--- /dev/null
+++ test/CodeGen/ARM/shift-combine.ll
@@ -0,0 +1,26 @@
+; RUN: llc -mtriple=armv7-linux-gnueabihf %s -o - | FileCheck %s
+
+ at array = weak global [4 x i32] zeroinitializer
+
+define i32 @test_lshr_and1(i32 %x) {
+;CHECK-LABEL: test_lshr_and1
+;CHECK-NOT lsr
+;CHECK-NOT lsl
+  %tmp2 = lshr i32 %x, 2
+  %tmp3 = and i32 %tmp2, 3
+  %tmp4 = getelementptr [4 x i32], [4 x i32]* @array, i32 0, i32 %tmp3
+  %tmp5 = load i32, i32* %tmp4, align 4
+  ret i32 %tmp5
+}
+define i32 @test_lshr_and2(i32 %x) {
+entry:
+;CHECK-LABEL: test_lshr_and2:
+;CHECK-NOT movw
+;CHECK-NOT and
+  %a = and i32 %x, 65534
+  %b = lshr i32 %a, 1
+  %c = and i32 %x, 65535
+  %d = lshr i32 %c, 1
+  %e = add i32 %b, %d
+  ret i32 %e
+}
Index: test/CodeGen/Thumb2/machine-licm.ll
===================================================================
--- test/CodeGen/Thumb2/machine-licm.ll
+++ test/CodeGen/Thumb2/machine-licm.ll
@@ -85,19 +85,17 @@
 ; CHECK-LABEL: t3:
 bb.nph:
 ; CHECK: bb.nph
-; CHECK: movw {{(r[0-9])|(lr)}}, #32768
+; CHECK: movw {{(r[0-9]+)|(lr)}}, #32768
 ; CHECK: movs {{(r[0-9]+)|(lr)}}, #0
 ; CHECK: movw [[REGISTER:(r[0-9]+)|(lr)]], #16386
-; CHECK: movw {{(r[0-9]+)|(lr)}}, #65534
 ; CHECK: movt {{(r[0-9]+)|(lr)}}, #65535
   br label %bb
 
 bb:                                               ; preds = %bb, %bb.nph
 ; CHECK: bb
 ; CHECK: eor.w
 ; CHECK: eorne.w {{(r[0-9])|(lr)}}, {{(r[0-9])|(lr)}}, [[REGISTER]]
 ; CHECK-NOT: eor
-; CHECK: and
   %data_addr.013 = phi i8 [ %data, %bb.nph ], [ %8, %bb ] ; <i8> [#uses=2]
   %crc_addr.112 = phi i16 [ %crc, %bb.nph ], [ %crc_addr.2, %bb ] ; <i16> [#uses=3]
   %i.011 = phi i8 [ 0, %bb.nph ], [ %7, %bb ]     ; <i8> [#uses=1]
Index: lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -4544,16 +4544,20 @@
   ConstantSDNode *BinOpCst = getAsNonOpaqueConstant(LHS->getOperand(1));
   if (!BinOpCst) return SDValue();
 
-  // FIXME: disable this unless the input to the binop is a shift by a constant.
-  // If it is not a shift, it pessimizes some common cases like:
-  //
-  //    void foo(int *X, int i) { X[i & 1235] = 1; }
-  //    int bar(int *X, int i) { return X[i & 255]; }
+  // FIXME: disable this unless the input to the binop is a shift by a constant
+  // or is copy/select.Enable this in other cases when figure out it's exactly profitable.
   SDNode *BinOpLHSVal = LHS->getOperand(0).getNode();
-  if ((BinOpLHSVal->getOpcode() != ISD::SHL &&
-       BinOpLHSVal->getOpcode() != ISD::SRA &&
-       BinOpLHSVal->getOpcode() != ISD::SRL) ||
-      !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1)))
+  bool isShift = BinOpLHSVal->getOpcode() == ISD::SHL ||
+                 BinOpLHSVal->getOpcode() == ISD::SRA ||
+                 BinOpLHSVal->getOpcode() == ISD::SRL;
+  bool isCopyOrSelect = BinOpLHSVal->getOpcode() == ISD::CopyFromReg ||
+                        BinOpLHSVal->getOpcode() == ISD::SELECT;
+
+  if ((!isShift || !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1))) &&
+      !isCopyOrSelect)
+    return SDValue();
+
+  if (isCopyOrSelect && N->hasOneUse())
     return SDValue();
 
   EVT VT = N->getValueType(0);


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