[PATCH] D27779: [ARM] More aggressive matching for vpadd and vpaddl.

[Eli Friedman via Phabricator via llvm-commits]

efriedma added inline comments.


================
Comment at: lib/Target/ARM/ARMISelLowering.cpp:9219
+  if ((N0.getOpcode() == ARMISD::VUZP ||
+      (N0.getOpcode() == ARMISD::VTRN && N0.getValueType() == MVT::v2i32)) &&
+      N0.getNode() == N1.getNode() &&
----------------
rengolin wrote:
> Why `v2i32` only? I can see from your tests that this also matches `i8`, so I'm suspecting this is already extended by the selection dag before getting here?
> 
> Also, `VPADD` works with `float`s, too.
This conditional is kind of awkward; I really want to just look for VUZP, but there is no v2i32 VUZP.

(The float vpadd isn't quite the same thing, but I guess I can look into it.)


================
Comment at: lib/Target/ARM/ARMISelLowering.cpp:9256
+        N00.getNode() == N10.getNode() &&
+        N00 != N10 && N00.getValueType().is64BitVector() &&
+        N0.getValueType().is128BitVector()) {
----------------
rengolin wrote:
> `VPADDL` works on D and Q regs, not Q only.
Yes... but in that case the type of `N00` would be a 32-bit vector, and the whole thing kind of explodes due to the way legalization works.  I'll include a testcase for reference.


Repository:
  rL LLVM

https://reviews.llvm.org/D27779