[llvm] r290193 - AMDGPU: Allow 16-bit types in inline asm constraints
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Tue Dec 20 11:06:13 PST 2016
Author: arsenm
Date: Tue Dec 20 13:06:12 2016
New Revision: 290193
URL: http://llvm.org/viewvc/llvm-project?rev=290193&view=rev
Log:
AMDGPU: Allow 16-bit types in inline asm constraints
Added:
llvm/trunk/test/CodeGen/AMDGPU/inlineasm-16.ll
Modified:
llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp
Modified: llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp?rev=290193&r1=290192&r2=290193&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp Tue Dec 20 13:06:12 2016
@@ -4382,6 +4382,7 @@ SITargetLowering::getRegForInlineAsmCons
default:
return std::make_pair(0U, nullptr);
case 32:
+ case 16:
return std::make_pair(0U, &AMDGPU::SReg_32_XM0RegClass);
case 64:
return std::make_pair(0U, &AMDGPU::SGPR_64RegClass);
@@ -4396,6 +4397,7 @@ SITargetLowering::getRegForInlineAsmCons
default:
return std::make_pair(0U, nullptr);
case 32:
+ case 16:
return std::make_pair(0U, &AMDGPU::VGPR_32RegClass);
case 64:
return std::make_pair(0U, &AMDGPU::VReg_64RegClass);
Added: llvm/trunk/test/CodeGen/AMDGPU/inlineasm-16.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/inlineasm-16.ll?rev=290193&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/inlineasm-16.ll (added)
+++ llvm/trunk/test/CodeGen/AMDGPU/inlineasm-16.ll Tue Dec 20 13:06:12 2016
@@ -0,0 +1,41 @@
+; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
+; RUN: not llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=SICI %s
+; RUN: not llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=SICI %s
+
+; GCN-LABEL: {{^}}s_input_output_i16:
+; SICI: error: couldn't allocate output register for constraint 's'
+; SICI: error: couldn't allocate input reg for constraint 's'
+define void @s_input_output_i16() #0 {
+ %v = tail call i16 asm sideeffect "s_mov_b32 $0, -1", "=s"()
+ tail call void asm sideeffect "; use $0", "s"(i16 %v) #0
+ ret void
+}
+
+; GCN-LABEL: {{^}}v_input_output_i16:
+; SICI: error: couldn't allocate output register for constraint 'v'
+; SICI: error: couldn't allocate input reg for constraint 'v'
+define void @v_input_output_i16() #0 {
+ %v = tail call i16 asm sideeffect "v_mov_b32 $0, -1", "=v"() #0
+ tail call void asm sideeffect "; use $0", "v"(i16 %v)
+ ret void
+}
+
+; GCN-LABEL: {{^}}s_input_output_f16:
+; SICI: error: couldn't allocate output register for constraint 's'
+; SICI: error: couldn't allocate input reg for constraint 's'
+define void @s_input_output_f16() #0 {
+ %v = tail call half asm sideeffect "s_mov_b32 $0, -1", "=s"() #0
+ tail call void asm sideeffect "; use $0", "s"(half %v)
+ ret void
+}
+
+; GCN-LABEL: {{^}}v_input_output_f16:
+; SICI: error: couldn't allocate output register for constraint 'v'
+; SICI: error: couldn't allocate input reg for constraint 'v'
+define void @v_input_output_f16() #0 {
+ %v = tail call half asm sideeffect "v_mov_b32 $0, -1", "=v"() #0
+ tail call void asm sideeffect "; use $0", "v"(half %v)
+ ret void
+}
+
+attributes #0 = { nounwind }
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