[PATCH] D27990: [Thumb] Add support for tMUL in the compare instruction peephole optimizer

Sjoerd Meijer via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue Dec 20 07:41:34 PST 2016


SjoerdMeijer created this revision.
SjoerdMeijer added reviewers: jmolloy, rengolin, dexonsmith, t.p.northover, rovka.
SjoerdMeijer added a subscriber: llvm-commits.

We also want to optimise tests like this: return a*b == 0.  The MULS instruction is flag setting, so we don't need the CMP instruction but can instead branch on the result of the MULS. The generated instructions sequence for this example was: MULS, MOVS, MOVS, CMP. The MOVS instruction load the boolean values resulting from the select instruction, but these MOVS instructions are flag setting and were thus preventing this optimisation. Now we first reorder and move the MULS to before the CMP and generate sequence MOVS, MOVS, MULS, CMP so that the optimisation could still be triggered. Reordering of the MULS and MOVS is safe to do because the subsequent MOVS instructions just set the CPSR register and don't use it, i.e. the CPSR is dead.


https://reviews.llvm.org/D27990

Files:
  lib/Target/ARM/ARMBaseInstrInfo.cpp
  test/CodeGen/ARM/mul-cmp-peephole.ll

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